FPGA Verilog XOR gate CONTROL structural design Xilinx spartan 3

This video is part of a series to design a Controlled Datapath using a structural approach in Verilog. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as instructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

The complete vhdl video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

XOR GATE CONTROL

 module nbit_xor_gate  
 #(parameter N = 4)  
 (  
 input [N-1:0] a,  
 input b,  
 output [N-1:0]f  
   );  
 genvar i;  
 generate  
           for(i=0;i<N;i=i+1)  
           begin: xor_instantiation  
             xor_gate xor_i(.a(a[i]),.b(b),.f(f[i]));  
           end  
 endgenerate            
 endmodule  

XOR GATE MODULE

 module xor_gate(  
   input a,  
   input b,  
   output f  
   );  
 assign f= a ^ b;  
 endmodule  
 // 1 as long as both inputs are different  
 //a b f  
 //0 0 0  
 //0 1 1  
 //1 0 1  
 //1 1 0  

TUTORIAL ON HOW TO ADD TIMING CONTRAINTS IN A MODULE

 #8I/Os_2  
 NET "a[0]" LOC = "p94" ;  
 NET "a[1]" LOC = "p93" ;  
 NET "a[2]" LOC = "p92" ;  
 NET "a[3]" LOC = "p91" ;  
 NET "b" LOC = "p88" ;  
 #16I/Os_1  
 NET "f[0]" LOC = "p126" ;  
 NET "f[1]" LOC = "p125" ;  
 NET "f[2]" LOC = "p124" ;  
 NET "f[3]" LOC = "p123" ;