FPGA Verilog four bit arithmetic unit structural design xilinx spartan 3

This video is part of a series to design a Controlled Datapath using a structural approach in Verilog. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as instructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

The complete vhdl video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

DOWNLOAD FILES <=

FOUR BIT ARITHMETIC UNIT STRUCTURAL DESIGN  
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module four_bit_arithmetic_unit
#(parameter N=4)

(
input [N-1:0]InA,
input [N-1:0]InB,
input [1:0]Control,
output [N-1:0]Sum,
output C_out
);
//assign InA =assig_to_A;
wire [N-1:0]mux_to_addersub;

nbit_two_input_multiplexer mux_component(4'b0001,InB,Control[0],mux_to_addersub);
nbit_adder_subtractor add_subtractor_component(InA,mux_to_addersub,Control[1],Sum,C_out);

endmodule


//Control    arithmetic function
// 00             A+1
// 01             A+B
// 10             A-1
// 11             A-B  

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FOUR BIT TWO INPUT MULTIPLEXER STRUCTURAL DESIGN
----------------------------------------------------------------------------------------------------------------

module nbit_two_input_multiplexer

#(parameter N=4)

(input [N-1:0]bin0,
input [N-1:0]bin1,
input sel,
output [N-1:0]mux_out);


genvar i;

  generate

      for (i=0;i begin: generate_mux
               two_input_multiplexer mux(.bin0(bin0[i]),.bin1(bin1[i]),.sel(sel),.mux_out(mux_out[i]));        

          end

  endgenerate

endmodule

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1 BIT TWO INPUT MULTIPLEXER
----------------------------------------------------------------------------------------------------------------

module two_input_multiplexer(
    input wire bin0,
    input wire bin1,
input wire sel,
    output mux_out
    );

                  //if select is 0 chose bin0 otherwise bin1  
assign mux_out = sel ? bin1 : bin0 ;

endmodule

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ADDER SUBTRACTOR TOP MODULE
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module nbit_adder_substractor
#(parameter N=4)
( input [N-1:0]InA,
input [N-1:0]InB,
input Control,
output [N-1:0]Sum,
output C_out

   );

wire [N-1:0]xor_to_adder;

four_bit_LAC_adder adder_component(InA,xor_to_adder,Control,Sum,C_out);
nbit_xor_gate_control xor_componet(InB,Control,xor_to_adder);

endmodule

FOUR BIT CARRY LOOK AHEAD ADDER COMPONENT
----------------------------------------------------------------------------------------------------------------



module four_bit_LAC_adder(
input [3:0]InA,
input [3:0]InB,
input Cin,
output [3:0]sum,
output Cout    );

wire [3:0]C_terms;

four_bit_LAC LAC_component(InA[3:0],InB[3:0],Cin,C_terms[3:0]);

nbit_full_adder full_adder_component(InA,InB,C_terms,sum,Cout);



endmodule

FOUR BIT CARRY LOOK AHEAD LOGIC COMPONENT
----------------------------------------------------------------------------------------------------------------

module four_bit_LAC(

input [3:0]InA,

input [3:0]InB,

input C_in,

output reg [3:0]C_terms

    );

wire [3:0]G;

wire [3:0]P;

assign  G[3:0] =  InA[3:0] & InB[3:0] ;//carry look ahead generate

assign  P[3:0] =  InA[3:0] | InB[3:0] ;//carry look ahead propagate

always @*

begin

C_terms[0] = C_in;

C_terms[1] =  G[0] | (P[0]& C_in); 

C_terms[2] =  G[1] | ( P[1] & G[0]) | (P[1] & P[0] & C_in);

C_terms[3] =  G[2] | ( P[2]& G[1])  | (P[2] & P[1] & G[0]) | (P[2] & P[1] & P[0] & C_in) ;

end

endmodule

FOUR BIT FULL ADDER

----------------------------------------------------------------------------------------------------------------

module nbit_full_adder

#(parameter N= 4)

(input [N-1:0]a,

input [N-1:0]b,

input [N-1:0]cin,

output [N-1:0]sum,

output cout

    );

wire [N-2:0]not_connected;

genvar i;

generate

for(i=0;i

begin: full_adder_instantiation

if (i

        begin

      full_adder full_adder_i(.a(a[i]),.b(b[i]),.cin(cin[i]),.s(sum[i]),.cout(not_connected[i]));

 end

else if(i==(N-1))

  begin

  full_adder full_adder_i(.a(a[i]),.b(b[i]),.cin(cin[i]),.s(sum[i]),.cout(cout));

end

end

endgenerate

endmodule

1 BIT FULL ADDER COMPONENT

----------------------------------------------------------------------------------------------------------------


module full_adder(
    input a,
    input b,
    input cin,
output s,
output cout
    );

wire to_xor,to_or0,to_or1;

half_adder half_adder_unit0(a,b,to_xor,to_or1);
half_adder half_adder_unit1(to_xor,cin,s,to_or0);
or_gate or_unit (to_or0,to_or1,cout);
endmodule


//cin a b c s
// 0  0 0 0 0
// 0  0 1 0 1
// 0  1 0 0 1
// 0  1 1 1 0
// 1  1 1 1 1      


HALF ADDER COMPONENT
----------------------------------------------------------------------------------------------------------------

module half_adder(

    input a,

    input b,

    output s,

    output c

    );

xor_gate xorGate_unit(a,b,s);

and_gate andgate_unit(a,b,c);

endmodule

//

//a b c s 

//0 0 0 0

//0 1 0 1

//1 0 0 1

//1 1 1 0     

XOR GATE COMPONENT

----------------------------------------------------------------------------------------------------------------

module xor_gate(

    input a,

    input b,

    output f

    );

assign f= a ^ b;

endmodule

// 1 as long as both inputs are different

//a b f

//0 0 0

//0 1 1

//1 0 1

//1 1 0    

AND GATE COMPONENT

----------------------------------------------------------------------------------------------------------------

module and_gate  (input wire a,

input wire b,

output wire f

                 ); 

assign f = a & b;

endmodule

XOR GATE CONTROL

----------------------------------------------------------------------------------------------------------------

module nbit_xor_gate_control

#(parameter N = 4)

(

input [N-1:0] a,

input b,

output [N-1:0]f

    );

genvar i;

generate

for(i=0;i

begin: xor_instantiation

   xor_gate xor_i(.a(a[i]),.b(b),.f(f[i]));

end

endgenerate

endmodule

// 1 as long as both inputs are different

//a b f

//0 0 0

//0 1 1

//1 0 1

//1 1 0

TUTORIAL ON HOW TO ADD TIMING CONSTRAINTS IN A MODULE

CONSTRAINT

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#8I/Os_2
NET "InB[0]"  LOC = "p88"  ;
NET "InB[1]"  LOC = "p87"  ;
NET "InB[2]"  LOC = "p86"  ;
NET "InB[3]"  LOC = "p85"  ;

#8I/Os_2
NET "InA[0]"  LOC = "p94"  ;
NET "InA[1]"  LOC = "p93"  ;
NET "InA[2]"  LOC = "p92"  ;
NET "InA[3]"  LOC = "p91"  ;

NET "Control[0]"  LOC = "p43"  ;
NET "Control[1]"  LOC = "p44"  ;

#16I/Os_1
NET "Sum[0]"  LOC = "p126"  ;
NET "Sum[1]"  LOC = "p125"  ;
NET "Sum[2]"  LOC = "p124"  ;
NET "Sum[3]"  LOC = "p123"  ;
NET "C_out"  LOC = "p122"  ;