FPGA Verilog 1 bit two input multiplexer Xilinx Spartan 3 development board code

This video is part of a series to design a Controlled Datapath using a structural approach in Verilog. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as instructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

The complete vhdl video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

 module two_input_multiplexer(  
   input wire bin0,  
   input wire bin1,  
       input wire sel,  
   output mux_out  
   );  
          //if select is 0 chose bin0 otherwise bin1    
 assign mux_out = sel ? bin1 : bin0 ;  
 endmodule  

CONSTRAINT FILE

 #8I/Os_2  
 NET "bin0" LOC = "p94" ;  
 NET "bin1" LOC = "p93" ;  
 NET "sel" LOC = "p54" ;  
 #16I/Os_1  
 NET "mux_out" LOC = "p126" ;