Verilog FPGA mod m counter circut test at 1Hz clk implemented in Xilinx Spartan 3 development board + code

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The mod m counter increases the count at each rising edge of the clock. The value of M can be adjusted to reach any value and the constant N needs to also be adjusted to make sure that we can allocate space for the binary count. In this project I use a count of 4 bits so the count can reach till binary 15 however as I am using only one display I set the counter M =10 . The counter increases up to the value of M-1 so the highest value it can reach is 9.

MOD M COUNTER MODULE

 // Listing 4.11  
 module mod_m_counter  
   #(  
   parameter N=4, // number of bits in counter 1111   
        M=10 // mod-M  
   )  
   (  
   input wire clk, reset,  
   output wire max_tick,  
   output wire [N-1:0] q,  
       output wire [N-1:0]an,  
       output wire [7:0] sseg  
   );  
   //signal declaration  
   reg [N-1:0] r_reg;  
   wire [N-1:0] r_next;  
 sseg_display sseg_unit(.addr(r_reg),.an(an),.sseg(sseg));       
   // body  
   // register  
   //posedge transition from 0 to 1, negedge transition from 1 to 0   
      always @(posedge clk, posedge reset)  
    if (reset)  
      r_reg <= 0;  
    else  
      r_reg <= r_next;  
   // next-state logic      true  false  
      assign r_next = (r_reg==(M-1)) ? 0 : r_reg + 1;  
   // output logic  
   assign q = r_reg;  
      //end of the count?        true  false             
   assign max_tick = (r_reg==(M-1)) ? 1'b1 : 1'b0;  
      assign an=4'b1000;  
 endmodule  

SEVEN SEGMENT DISPLAY MODULE

 module sseg_display(  
 input wire [3:0]addr,  
 input wire [3:0]an,  
 output reg [7:0]sseg  
   );  
 always @*  
      begin  
       case(addr)  
            4'b0000: sseg[7:0] =8'b11000000; //0    
         4'b0001: sseg[7:0] =8'b11111001; //1    
         4'b0010: sseg[7:0] =8'b10100100; // 2   
         4'b0011: sseg[7:0] =8'b10110000; // 3  
         4'b0100: sseg[7:0] =8'b10011001; // 4  
         4'b0101: sseg[7:0] =8'b10010010; // 5  
         4'b0110: sseg[7:0] =8'b10000010; // 6  
         4'b0111: sseg[7:0] =8'b11111000; // 7  
         4'b1000: sseg[7:0] =8'b10000000; // 8  
         default: sseg[7:0] =8'b10010000; // 9  
         endcase  
                          end  
 endmodule  

CONSTRAINT FILE MODULE(check out my video to adding timing constrains)

 #8I/Os_2 (Input)  
 NET "reset" LOC = "p94" ;  
 #8I/Os_2 (Input)  
 NET "max_tick" LOC = "p116" ;  
 #16I/Os_1 (output)  
 NET "q[0]" LOC = "p126" ;  
 NET "q[1]" LOC = "p125" ;  
 NET "q[2]" LOC = "p124" ;  
 NET "q[3]" LOC = "p123" ;  
 #8I/Os_2 (cathods)  
 NET "an[0]" LOC = "p71" ;  
 NET "an[1]" LOC = "p75" ;  
 NET "an[2]" LOC = "p77" ;  
 NET "an[3]" LOC = "p82" ;  
 #16I/Os_2 seven segment display  
 NET "sseg[7]" LOC = "p60"  ;  
 NET "sseg[6]" LOC = "p63" ;  
 NET "sseg[5]" LOC ="p67"  ;  
 NET "sseg[4]" LOC ="p70" ;  
 NET "sseg[3]" LOC = "p74" ;  
 NET "sseg[2]" LOC = "p76"  ;  
 NET "sseg[1]" LOC = "p81"  ;  
 NET "sseg[0]" LOC = "p83" ;  
 #Created by Constraints Editor (xc3s250e-tq144-4) - 2017/08/08  
 NET "clk" LOC ="p54";#TNM_NET = clk;  
 #TIMESPEC TS_clk = PERIOD "clk" 10 MHz HIGH 50%;  

TUTORIAL ON HOW TO ADD CLOCK TIMING CONSTRAINTS IN A MODULE