FPGA VHDL 4 x 4 RAM memory behavioural - Circuit test xilinx spartan 3 waveshare development board

read was modified to 10 and write to 01

   

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4x4 RAM memory

 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- needed for CONV_INTEGER()
ENTITY RAM_memory IS PORT (
CE, WR: IN STD_LOGIC; --chip enable, write enable
A: IN STD_LOGIC_VECTOR(3 DOWNTO 0); --address
D: buffer STD_LOGIC_VECTOR(3 DOWNTO 0); --data
Input_signal: in STD_LOGIC_VECTOR(3 DOWNTO 0)); --data
END RAM_memory;
ARCHITECTURE Behavioral OF RAM_memory IS
BEGIN
PROCESS (CE, WR)
SUBTYPE cell IS STD_LOGIC_VECTOR(3 DOWNTO 0);
TYPE memArray IS array(0 TO 15) OF cell;
VARIABLE mem: memArray; --memory contents
VARIABLE ctrl: STD_LOGIC_VECTOR(1 DOWNTO 0);

BEGIN
ctrl := CE & Wr; -- group signals for CASE decoding
CASE ctrl IS
WHEN "10" => -- read
D <= mem(CONV_INTEGER(A));-- fn TO convert from bit vector TO integer


WHEN "01" => -- write
mem(CONV_INTEGER(A)) := Input_signal;-- fn TO convert from bit vector TO integer

WHEN OTHERS => -- invalid or not enable
D <= (OTHERS => '0');
END CASE;

END PROCESS;
END Behavioral;