In order to write programs you need to understand how to manipulate the ROM memory module I recommend you to watch my tutorial. It is long but I tried to explain step by step how I designed the ones shifter:
Lab sheets:
Each of the components in this design has been tested on the development board:
 |
| CONTROLLED DATAPATH |
 |
| CONTROLLED DATAPATH CONNECTIONS |
 |
| CONTROLLED DATAPATH INTERNAL MODULES |
 |
| CONTROLLER INTERNAL MUDULES |
 |
| CONTROLLER RTL SCHEMATIC |
 |
| DATAPATH STRUCTURE |
 |
| DATAPATH INTERNAL MUDULES RTL SCHEMATIC |
 |
| CONTROLLED DATAPATH INPUT/OUTPUT PORTS |
FPGA VHDL CONTROLLED DATAPATH TOP MODULE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Controlled_datapath is
generic(n:positive:=4);
Port ( start : in STD_LOGIC;
alt : in STD_LOGIC;
clk : in STD_LOGIC;
asynchronousreset : in STD_LOGIC;
datain : in STD_LOGIC_VECTOR (3 downto 0);
done : out STD_LOGIC;
dataout : inout STD_LOGIC_VECTOR (3 downto 0));
end Controlled_datapath;
architecture Behavioral of Controlled_datapath is
component CONTROLLER
--generic(n:positive:=4);
Port ( start : in STD_LOGIC;
datanotzero : in STD_LOGIC;
alt :in std_logic;
clk : in STD_LOGIC;
asynchronousreset : in STD_LOGIC;
datapathcontrol : out STD_LOGIC_VECTOR (19 downto 0);
done : out STD_LOGIC);
end component;
component DATA_PATH
generic(n:positive:=4);
Port ( Input : in STD_LOGIC_VECTOR (3 downto 0);
S : in STD_LOGIC;
Write_address : in STD_LOGIC_VECTOR (2 downto 0);
Write_enable : in STD_LOGIC;
Read_address_A : in STD_LOGIC_VECTOR (2 downto 0);
Read_Enable_A : in STD_LOGIC;
Read_address_B : in STD_LOGIC_VECTOR (2 downto 0);
Read_Enable_B : in STD_LOGIC;
Function_arith_or_logic : in STD_LOGIC_VECTOR (2 downto 0);
G : in STD_LOGIC_VECTOR (2 downto 0);
Status : out STD_LOGIC;
en : in STD_LOGIC;
clk : in STD_LOGIC;
Output : out STD_LOGIC_VECTOR (3 downto 0));
end component;
SIGNAL controlwords : std_logic_vector(19 downto 0);
SIGNAL datanotzero : std_logic;
begin
--datanotzero comes from data path 0 (output register part)
firstpart: CONTROLLER port map(start,datanotzero,alt,clk,asynchronousreset,controlwords,done);
secondpart: DATA_PATH port map(datain,controlwords(19),controlwords(18 downto 16),controlwords(15),controlwords(14 downto 12),controlwords(11),controlwords(10 downto 8),controlwords(7),controlwords(6 downto 4),controlwords(3 downto 1),datanotzero,controlwords(0),clk,dataout);
end Behavioral;
CONTROLLER
-----------------------------working-------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CONTROLLER is
Port ( start : in STD_LOGIC;
datanotzero : in STD_LOGIC;
alt :in std_logic;
clk : in STD_LOGIC;
asynchronousreset : in STD_LOGIC;
datapathcontrol : out STD_LOGIC_VECTOR (19 downto 0);
done : out STD_LOGIC);
end CONTROLLER;
architecture Behavioral of CONTROLLER is
component fourinputmux
port (a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
control : in std_logic_vector(1 downto 0);
output : out std_logic
);
end component;
component functiondecodelogic
Port (Condition : in STD_LOGIC;
Functions : in STD_LOGIC_VECTOR (1 downto 0);
Load_Count_OUT : out STD_LOGIC;
Enable_OUT: out STD_LOGIC);
end component;
component nbitsynchronouscounterwithparallelload
Port ( dinputs : in STD_LOGIC_VECTOR (3 downto 0);
loadcount : in STD_LOGIC;
countenable : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
qoutputs : inout STD_LOGIC_VECTOR (3 downto 0));
end component;
component ROM_memory
Port ( address: in STD_LOGIC_VECTOR(3 downto 0);
condition_select: out STD_LOGIC_VECTOR(1 downto 0);
Functions: out STD_LOGIC_VECTOR(1 downto 0);
d_out: out STD_LOGIC_VECTOR(19 downto 0);
done : out STD_LOGIC;
Branch_ADDRESS_M : out STD_LOGIC_VECTOR(3 downto 0)
);
end component;
signal fromromconditionselect,fromromtofunction:std_logic_vector(1 downto 0);
signal branchaddress,torom:std_logic_vector(3 downto 0);
signal tofuctiondecode,toloadcount,toenable:std_logic;
begin
A: fourinputmux port map('1',start,datanotzero,alt,fromromconditionselect,tofuctiondecode);
B: functiondecodelogic port map(tofuctiondecode,fromromtofunction,toloadcount,toenable);
C: nbitsynchronouscounterwithparallelload port map(branchaddress,toloadcount,toenable,clk,asynchronousreset,torom);
D:ROM_memory port map(torom,fromromconditionselect,fromromtofunction,datapathcontrol,done,branchaddress);
end Behavioral;
-----------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity functiondecodelogic is
Port ( Condition : in STD_LOGIC;
Functions : in STD_LOGIC_VECTOR (1 downto 0);
Load_Count_OUT : out STD_LOGIC;
Enable_OUT: out STD_LOGIC);
end functiondecodelogic;
architecture Behavioral of functiondecodelogic is
begin
PROCESS(Functions,Condition)IS
BEGIN
CASE Functions IS
WHEN "00" => -- FUNCTION is at CA : Count always
Load_Count_OUT <= '0' after 7ns; -- theses two statements will make the state increment naturally
Enable_OUT <= '1';
WHEN "01" => -- FUNCTION is at CC : Count depends on the Condition
Load_Count_OUT <= '0' after 7ns; -- thses two statements will make the state increment if codition is true otherwise stay on the state
Enable_OUT <= Condition ;
WHEN "10" => -- FUNCTION is at BC : branch depends on the Condition
Load_Count_OUT <= '1' after 7ns; -- thses two statements will make the state change to seperate state
Enable_OUT <= Condition ;
WHEN "11" => -- FUNCTION is at CBC : Count or Branch Conditional
Load_Count_OUT <= Condition; -- inavlid input is not used
Enable_OUT <= '1';
WHEN OTHERS =>
--FUNCTION---VALUE--
--------------------
----CA---- ---00----
----CC---- ---01----
----BC---- ---10----
----CBC--- ---11----
END CASE;
END PROCESS;
end Behavioral;
------------------------------------------------
package timing is
-- Change the first two constants to match your system requirements...
constant Clock_Freq : real := 0.5;
constant Sample_Rate : real := 100.0;
-- These are calculated from the above, so stay correct when you make changes
constant Divide : natural := natural(Clock_Freq / Sample_Rate);
-- sometimes you also need a period, e.g. in a testbench.
constant clock_period : time := 100 sec / Clock_Freq;
end package timing;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.timing.all;
entity nbitsynchronouscounterwithparallelload is
generic(n:positive:=4);
Port ( dinputs : in STD_LOGIC_VECTOR (n-1 downto 0);
loadcount : in STD_LOGIC;
countenable : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
qoutputs : inout STD_LOGIC_VECTOR (n-1 downto 0);
tomultiplexer:inout STD_LOGIC_VECTOR (n-1 downto 0));
end nbitsynchronouscounterwithparallelload;
architecture Behavioral of nbitsynchronouscounterwithparallelload is
component nbitincrementer
Port ( ina : in STD_LOGIC_VECTOR (n-1 downto 0);
cin : in STD_LOGIC;
sum : out STD_LOGIC_VECTOR (n-1 downto 0);
cout : out STD_LOGIC);
end component;
component nbittwoinputmux
generic(n:positive:=4);
Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0);
InB : in STD_LOGIC_VECTOR (n-1 downto 0);
Control : in STD_LOGIC;
Output : out STD_LOGIC_VECTOR (n-1 downto 0));
end component;
component nbitregister
generic(n:positive:=4);
Port ( Dinputs : in STD_LOGIC_VECTOR (n-1 downto 0);
clk : in STD_LOGIC;
reset : in STD_LOGIC;
preset : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (n-1 downto 0);
qnot : out STD_LOGIC_VECTOR (n-1 downto 0)
);
end component;
signal notconnected:std_logic;
signal feedback,tomux,toreg,notconnected2:std_logic_vector(n-1 downto 0);
begin
qoutputs<=feedback;
A: nbitincrementer port map(feedback,countenable,tomux,notconnected);
B: nbittwoinputmux port map(tomux,dinputs,loadcount,toreg);
C: nbitregister port map(toreg,clk,reset,'0',feedback,notconnected2);
tomultiplexer<=tomux;
end Behavioral;
---------------------------------
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity nbitincrementer is
generic(n:positive:=4);
Port ( ina : in STD_LOGIC_VECTOR (n-1 downto 0);
cin : in STD_LOGIC;
sum : out STD_LOGIC_VECTOR (n-1 downto 0);
cout : out STD_LOGIC);
end nbitincrementer;
architecture Behavioral of nbitincrementer is
component halfadder
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end component;
signal carryouttob:std_logic_vector(n-2 downto 0);
begin
inst:for i in n-1 downto 0 generate
if0:if i=0 generate
A: halfadder port map(ina(i),cin,sum(i),carryouttob(i));
end generate;
if1:if i/=0 and i/=n-1 generate
A: halfadder port map(ina(i),carryouttob(i-1),sum(i),carryouttob(i));
end generate;
if2:if i=n-1 generate
A: halfadder port map(ina(i),carryouttob(i-1),sum(i),cout);
end generate;
end generate;
end Behavioral;
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity halfadder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end halfadder;
architecture Behavioral of halfadder is
begin
sum<= a xor b;
cout<=a and b;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity nbitregister is
generic(n:positive:=4);
Port ( Dinputs : in STD_LOGIC_VECTOR (n-1 downto 0);
clk : in STD_LOGIC;
reset : in STD_LOGIC;
preset : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (n-1 downto 0);
qnot : out STD_LOGIC_VECTOR (n-1 downto 0)
);
end nbitregister;
architecture Behavioral of nbitregister is
component D_flipflop is
port (d, clk, reset, preset : in std_logic;
q,qnot: out std_logic);
end component;
begin
inst:for i in n-1 downto 0 generate
A: D_flipflop port map(Dinputs(i),clk,reset,preset,q(i),qnot(i));
end generate;
end Behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity D_flipflop is
port (d, clk, reset, preset : in std_logic;
q,qnot: out std_logic);
end D_flipflop;
architecture behav of D_flipflop is
begin
process (clk, reset, preset) begin
if (reset = '1') then
q <= '0';
qnot<='1';
elsif (preset = '1') then
q <= '1';
qnot<='0';
elsif (clk'event and clk = '1') then
q <= d;
qnot<= not d;
end if;
end process;
end behav;
----------------------------------
DATAPATH
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity twoinputmultiplexer is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : in STD_LOGIC;
output : out STD_LOGIC);
end twoinputmultiplexer;
architecture Behavioral of twoinputmultiplexer is
begin
process(a,b,s)
begin
case s is
when '0' => output <= a;
when '1' => output <= b;
when others => output <= b;
end case;
end process;
end Behavioral;
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity nbitregloadhold is
generic(n:positive:=4);
Port ( Dinputs : in STD_LOGIC_VECTOR (n-1 downto 0);
loadhold : in STD_LOGIC;
CLK : in STD_LOGIC;
reset : in STD_LOGIC;
preset : in STD_LOGIC;
qoutputs : inout STD_LOGIC_VECTOR (n-1 downto 0));
end nbitregloadhold;
architecture Behavioral of nbitregloadhold is
component nbitregister
generic(n:positive:=4);
Port ( Dinputs : in STD_LOGIC_VECTOR (n-1 downto 0);
clk : in STD_LOGIC;
reset : in STD_LOGIC;
preset : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (n-1 downto 0);
qnot : out STD_LOGIC_VECTOR (n-1 downto 0));
end component;
component nbittwoinputmux
generic(n:positive:=4);
Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0);
InB : in STD_LOGIC_VECTOR (n-1 downto 0);
Control : in STD_LOGIC;
Output : out STD_LOGIC_VECTOR (n-1 downto 0));
end component;
signal toreg,dummyq:std_logic_vector(n-1 downto 0);
begin
A: nbittwoinputmux port map(qoutputs,Dinputs,loadhold,toreg);
B: nbitregister port map(toreg, CLK, reset,preset,qoutputs, dummyq);
end Behavioral;
---------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity orgate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
f : out STD_LOGIC);
end orgate;
architecture Behavioral of orgate is
begin
f<=a or b;
end Behavioral;
----------------------------------------------
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
---------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---------------------------------------------------------
-- Top level design
---------------------------------------------------------
entity nBitShiftRotateM is
generic(n:positive:=4);
Port (Data_In1 : in std_logic_vector(n-1 downto 0);
Data_In2 : in std_logic_vector(n-1 downto 0);
Right_In : in std_logic;
Right_Select : in std_logic;
Left_In : in std_logic;
Left_Select : in std_logic;
Control : in std_logic_vector (1 downto 0);
Output : out std_logic_vector (n-1 downto 0));
end nBitShiftRotateM;
---------------------------------------------------------
-- Top level design
---------------------------------------------------------
architecture Behavioral of nBitShiftRotateM is
--COMPONENT: two_input_mux
component twoinputmultiplexer
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : in STD_LOGIC;
output : out STD_LOGIC);
end component;
--END COMPONENT: two_input_mux
--COMPONENT: fourInputMux
component fourinputmux
port (
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
control : in std_logic_vector(1 downto 0);
output : out std_logic
);
end component;
--END COMPONENT: fourInputMux
--SIGNALS
signal muxToFour, muxToFourZero: std_logic;
begin
inst: for i in n-1 downto 0 generate
if1: if i = n-1 generate
twoMux: twoinputmultiplexer port map (Data_In1(0),Left_In, Left_Select, muxToFour);
fourMuxTwo: fourinputmux port map (Data_In1(i), Data_In1(i-1), muxToFour, Data_In2(i), Control, Output(i));
end generate;
--When i is 0
if2: if i = 0 generate
twoMuxZero: twoinputmultiplexer port map (Data_In1(n-1),Right_In, Right_Select, muxToFourZero);
fourMuxZero: fourinputmux port map (Data_In1(0),muxToFourZero, Data_In1(1), Data_In2(0), Control, Output(0));
end generate;
--Else generate
if3: if ((i/=0) and (i/=n-1)) generate
fourMuxMid: fourinputmux port map (Data_In1(i),Data_In1(i-1), Data_In1(i+1), Data_In2(i), Control, Output(i));
end generate;
end generate;
end Behavioral;
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity shiftcontrollogic is
Port ( input : in STD_LOGIC_VECTOR (2 downto 0);
output : out STD_LOGIC_VECTOR (1 downto 0));
end shiftcontrollogic;
architecture Behavioral of shiftcontrollogic is
begin
output(0)<= (not input(2)) and (input(1) or input(0));
output(1)<= ( input(2)) and (input(1) or input(0));
end Behavioral;
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- ENTITY
entity four_bit_shifter is
Port ( Data_In : in std_logic_vector(3 downto 0);
G : in std_logic_vector(2 downto 0);
Output : out std_logic_vector(3 downto 0));
end four_bit_shifter;
-- ARCHITECTURE
architecture Behavioral of four_bit_shifter is
-- COMPONENTS
component nBitShiftRotateM
generic(n:positive:=4);
Port (Data_In1 : in std_logic_vector(n-1 downto 0);
Data_In2 : in std_logic_vector(n-1 downto 0);
Right_In : in std_logic;
Right_Select : in std_logic;
Left_In : in std_logic;
Left_Select : in std_logic;
Control : in std_logic_vector (1 downto 0);
Output : out std_logic_vector (n-1 downto 0));
end component;
component shiftcontrollogic
Port ( input : in STD_LOGIC_VECTOR (2 downto 0);
output : out STD_LOGIC_VECTOR (1 downto 0));
end component;
-- SIGNAL
signal shift_control : std_logic_vector (1 downto 0);
begin
-- INSTANCES
-- instantiate a shift_control_logic device:
logic_device : shiftcontrollogic port map (G, shift_control);
-- instantiate an n-bit shift_rotate device with generic value "n"
-- mapped to a bit-width of 4. Note that the second data input is
-- connected directly to ground by using the 4-bit value "0000".
shift_device : nBitShiftRotateM generic map (4) port map (Data_In, "0000", G(0), G(1), G(0), G(1), shift_control, Output);
end Behavioral;
-----------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- ENTITY
entity four_bit_alu is
Port ( InA : in std_logic_vector(3 downto 0);
InB : in std_logic_vector(3 downto 0);
F : in std_logic_vector(2 downto 0);
Output : out std_logic_vector(3 downto 0);
C_out : out std_logic);
end four_bit_alu;
-- ARCHITECHTURE
architecture Behavioral of four_bit_alu is
component four_bit_arithmetic_unit
Port ( InA : in STD_LOGIC_VECTOR (3 downto 0);
InB : in STD_LOGIC_VECTOR (3 downto 0);
Control : in STD_LOGIC_VECTOR (1 downto 0);
Sum : out STD_LOGIC_VECTOR (3 downto 0);
C_out : out STD_LOGIC);
end component;
component nbitlogicunit
generic(n:positive:=4);
Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0);
InB : in STD_LOGIC_VECTOR (n-1 downto 0);
control : in STD_LOGIC_VECTOR (1 downto 0);
output : out STD_LOGIC_VECTOR (n-1 downto 0));
end component;
-- COMPONENTS:
component nbittwoinputmux
generic(n:positive:=4);
Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0);
InB : in STD_LOGIC_VECTOR (n-1 downto 0);
Control : in STD_LOGIC;
Output : out STD_LOGIC_VECTOR (n-1 downto 0));
end component;
-- SIGNALS
signal arith_to_mux, logic_to_mux : std_logic_vector (3 downto 0);
begin
-- INSTANCES
-- instantiate the arithemetic unit:
arith : four_bit_arithmetic_unit port map (InA, InB, F(1 downto 0), arith_to_mux, C_out);
-- instantiate the logic unit with a bit-width of 4 (map generic value "n" to 4)
logic : nbitlogicunit port map (InA, InB, F(1 downto 0), logic_to_mux);
-- instantiate the mux with a bit-width of 4 (map generic value "n" to 4)
mux : nbittwoinputmux port map (logic_to_mux,arith_to_mux, F(2), output);
end Behavioral;
-------------------------------------
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity four_bit_arithmetic_unit is
Port ( InA : in STD_LOGIC_VECTOR (3 downto 0);
InB : in STD_LOGIC_VECTOR (3 downto 0);
Control : in STD_LOGIC_VECTOR (1 downto 0);
Sum : out STD_LOGIC_VECTOR (3 downto 0);
C_out : out STD_LOGIC);
end four_bit_arithmetic_unit;
architecture Behavioral of four_bit_arithmetic_unit is
Component nbittwoinputmux
generic(n:positive:=4);
Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0);
InB : in STD_LOGIC_VECTOR (n-1 downto 0);
Control : in STD_LOGIC;
Output : out STD_LOGIC_VECTOR (n-1 downto 0));
end component;
component addersubstractor
generic(n:positive:=4);
Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0);
InB : in STD_LOGIC_VECTOR (n-1 downto 0);
control : in STD_LOGIC;
sum : out STD_LOGIC_VECTOR (n-1 downto 0);
cout : out STD_LOGIC);
end component;
signal muxtoadder:std_logic_vector(3 downto 0);
begin
A: nbittwoinputmux port map("0001",InB,Control(0),muxtoadder);
B: addersubstractor port map(InA,muxtoadder,Control(1),Sum,C_out);
end Behavioral;
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity addersubstractor is
generic(n:positive:=4);
Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0);
InB : in STD_LOGIC_VECTOR (n-1 downto 0);
control : in STD_LOGIC;
sum : out STD_LOGIC_VECTOR (n-1 downto 0);
cout : out STD_LOGIC);
end addersubstractor;
architecture Behavioral of addersubstractor is
component nbit_xor_contol is
Generic ( n : positive := 4 );
Port ( Input : in std_logic_vector(n-1 downto 0);
control : in std_logic;
Output : out std_logic_vector(n-1 downto 0));
end component;
component fourbitlacadder
generic(n:positive:=4);
Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0);
InB : in STD_LOGIC_VECTOR (n-1 downto 0);
cin : in STD_LOGIC;
sum : out STD_LOGIC_VECTOR (n-1 downto 0);
cout : out STD_LOGIC);
end component;
signal xorcontroltolacadder:std_logic_vector(n-1 downto 0);
begin
A: nbit_xor_contol port map(InB,control,xorcontroltolacadder);
B: fourbitlacadder port map(InA,xorcontroltolacadder,control,sum,cout);
end Behavioral;
-- ---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- ENTITY
entity nbit_xor_contol is
-- GENERIC VALUE:
Generic ( n : positive := 4 );
-- PORTS
Port ( Input : in std_logic_vector(n-1 downto 0);
control : in std_logic;
Output : out std_logic_vector(n-1 downto 0));
end nbit_xor_contol;
-- ARCHITECTURE
architecture Behavioral of nbit_xor_contol is
-- COMPONENTS
component xorgate
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
f : out STD_LOGIC);
end component;
begin
-- FOR LOOP
-- create an instance of a for loop called "inst"
inst : for i in n-1 downto 0 generate
-- generate n instances of the device "two_input_xor"
xor_gate_i : xorgate port map (Input(i), control, Output(i));
end generate;
end Behavioral;
-------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fourinputmux is
port (
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
control : in std_logic_vector(1 downto 0);
output : out std_logic
);
end fourinputmux ;
architecture Behavioral of fourinputmux is
begin
process(a,b,c,d,control)
begin
case control is
when "00" => output <= a;
when "01" => output <= b;
when "10" => output <= c;
when others => output <= d;
end case;
end process;
end Behavioral;
-------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity nbittwoinputmux is
generic(n:positive:=4);
Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0);
InB : in STD_LOGIC_VECTOR (n-1 downto 0);
Control : in STD_LOGIC;
Output : out STD_LOGIC_VECTOR (n-1 downto 0));
end nbittwoinputmux;
architecture Behavioral of nbittwoinputmux is
component twoinputmultiplexer
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : in STD_LOGIC;
output : out STD_LOGIC);
end component;
begin
inst: for i in n-1 downto 0 generate
A: twoinputmultiplexer port map(InA(i),InB(i),Control,Output(i));
end generate;
end Behavioral;
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity xorgate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
f : out STD_LOGIC);
end xorgate;
architecture Behavioral of xorgate is
begin
f<= a xor b;
end Behavioral;
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fourbitlacadder is
generic(n:positive:=4);
Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0);
InB : in STD_LOGIC_VECTOR (n-1 downto 0);
cin : in STD_LOGIC;
sum : out STD_LOGIC_VECTOR (n-1 downto 0);
cout : out STD_LOGIC);
end fourbitlacadder;
architecture Behavioral of fourbitlacadder is
component four_bit_LAC
Port ( InA : in std_logic_vector(3 downto 0);
InB : in std_logic_vector(3 downto 0);
C_In : in std_logic;
C_terms : out std_logic_vector(3 downto 0));
end component;
component nbitadder
generic(n:positive:=4);
Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0);
InB : in STD_LOGIC_VECTOR (n-1 downto 0);
C_terms : in STD_LOGIC_VECTOR (n-1 downto 0);
sum : out STD_LOGIC_VECTOR (n-1 downto 0);
c_out : out STD_LOGIC);
end component;
signal lactoadder:std_logic_vector(n-1 downto 0);
begin
A: four_bit_LAC port map(InA,InB,cin,lactoadder);
B: nbitadder port map(InA,InB,lactoadder,sum,cout);
end Behavioral;
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- ENTITY
entity four_bit_LAC is
Port ( InA : in std_logic_vector(3 downto 0);
InB : in std_logic_vector(3 downto 0);
C_In : in std_logic;
C_terms : out std_logic_vector(3 downto 0));
end four_bit_LAC;
-- ARCHITECTURE
architecture Behavioral of four_bit_LAC is
-- SIGNALS
signal G, P : std_logic_vector (3 downto 0);
begin
-- LOGIC ASSIGNMENTS
G <= InA and InB after 7 ns; -- look ahead "generate" terms
P <= InA or InB after 7 ns; -- look ahead "propagate" terms
-- look ahead "carry" terms:
C_terms(0) <= C_in;
C_terms(1) <= G(0) or (P(0) and C_in) after 14 ns;
C_terms(2) <= G(1) or (P(1) and G(0)) or (P(1) and P(0) and C_in) after 14 ns;
C_terms(3) <= G(2) or (P(2) and G(1)) or (P(2) and P(1) and G(0)) or (P(2) and P(1) and P(0) and C_in) after 14 ns;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity nbitadder is
generic(n:positive:=4);
Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0);
InB : in STD_LOGIC_VECTOR (n-1 downto 0);
C_terms : in STD_LOGIC_VECTOR (n-1 downto 0);
sum : out STD_LOGIC_VECTOR (n-1 downto 0);
c_out : out STD_LOGIC);
end nbitadder;
architecture Behavioral of nbitadder is
component fulladder
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end component;
signal not_connected: STD_LOGIC_VECTOR(n-2 downto 0);
begin
inst:for i in n-1 downto 0 generate
lastbit:if i=n-1 generate
A: fulladder port map (InA(i),InB(i),C_terms(i),sum(i),c_out);
end generate;
otherbits: if i/=n-1 generate
B: fulladder port map(InA(i),InB(i),C_terms(i),sum(i),not_connected(i));
end generate;
end generate;
end Behavioral;
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fulladder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end fulladder;
architecture Behavioral of fulladder is
signal xor1,and_1,and_2:std_logic;
begin
xor1<=a xor b;
sum<=xor1 xor cin;
and_1<=xor1 and cin;
and_2<=a and b;
cout<=and_1 or and_2;
end Behavioral;
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity nbitlogicunit is
generic(n:positive:=4);
Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0);
InB : in STD_LOGIC_VECTOR (n-1 downto 0);
control : in STD_LOGIC_VECTOR (1 downto 0);
output : out STD_LOGIC_VECTOR (n-1 downto 0));
end nbitlogicunit;
architecture Behavioral of nbitlogicunit is
component bitsliceLogicslice
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
control : in STD_LOGIC_VECTOR (1 downto 0);
output : out STD_LOGIC);
end component;
begin
inst: for i in n-1 downto 0 generate
A: bitsliceLogicslice port map(InA(i),InB(i),control,output(i));
end generate;
end Behavioral;
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bitsliceLogicslice is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
control : in STD_LOGIC_VECTOR (1 downto 0);
output : out STD_LOGIC);
end bitsliceLogicslice;
architecture Behavioral of bitsliceLogicslice is
component inverter
Port ( a : in STD_LOGIC;
f : out STD_LOGIC);
end component;
component andgate
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
f : out STD_LOGIC);
end component;
component orgate
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
f : out STD_LOGIC);
end component;
component xorgate
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
f : out STD_LOGIC);
end component;
component fourinputmux
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
control : in STD_LOGIC_VECTOR (1 downto 0);
output : out STD_LOGIC);
end component;
signal invertertomux,andtomux,xortomux,ortomux:std_logic;
begin
A1: inverter port map (a,invertertomux);
B1: andgate port map (a,b,andtomux);
C1: xorgate port map(a,b,xortomux);
D1: orgate port map(a,b,ortomux);
E1: fourinputmux port map (invertertomux,andtomux,xortomux,ortomux,control,output);
end Behavioral;
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity inverter is
Port ( a : in STD_LOGIC;
f : out STD_LOGIC);
end inverter;
architecture Behavioral of inverter is
begin
f<= not a;
end Behavioral;
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity andgate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
f : out STD_LOGIC);
end andgate;
architecture Behavioral of andgate is
begin
f<= a and b after 10 ns;
end Behavioral;
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fourInputOr is
Port ( INA : in STD_LOGIC;
INB : in STD_LOGIC;
INC : in STD_LOGIC;
IND : in STD_LOGIC;
OUTPUT : out STD_LOGIC);
end fourInputOr;
architecture Behavioral of fourInputOr is
component orgate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
f : out STD_LOGIC);
end component;
SIGNAL OR_SIG1, OR_SIG2 : std_logic;
begin
OR_1 : orgate port map (INA, INB, OR_SIG1 );
OR_2 : orgate port map (INC, IND, OR_SIG2 );
OR_3 : orgate port map (OR_SIG1 , OR_SIG2 , OUTPUT );
end Behavioral;
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity xorgate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
f : out STD_LOGIC);
end xorgate;
architecture Behavioral of xorgate is
begin
f<= a xor b;
end Behavioral;
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity orgate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
f : out STD_LOGIC);
end orgate;
architecture Behavioral of orgate is
begin
f<=a or b;
end Behavioral;
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity eightXnbitregisterfile is
generic(n:positive:=4);
Port ( Data_in : in STD_LOGIC_VECTOR (n-1 downto 0);
Read_address_A : in STD_LOGIC_VECTOR (2 downto 0);
Read_address_B : in STD_LOGIC_VECTOR (2 downto 0);
write_address : in STD_LOGIC_VECTOR (2 downto 0);
REA : in STD_LOGIC;
REB : in STD_LOGIC;
WE : in STD_LOGIC;
clk : in STD_LOGIC;
outA : out STD_LOGIC_VECTOR (n-1 downto 0);
outB : out STD_LOGIC_VECTOR (n-1 downto 0));
end eightXnbitregisterfile;
architecture Behavioral of eightXnbitregisterfile is
component three_to_eight_decoder
Port ( OE : in std_logic;
address : in std_logic_vector(2 downto 0);
O_outputs : out std_logic_vector(n-1 downto 0));
end component;
component nbitreggistercellfile
generic(n:positive:=4);
Port ( din : in STD_LOGIC_VECTOR (n-1 downto 0);
rea : in STD_LOGIC;
reb : in STD_LOGIC;
we : in STD_LOGIC;
clk : in STD_LOGIC;
outA : out STD_LOGIC_VECTOR (n-1 downto 0);
outB : out STD_LOGIC_VECTOR (n-1 downto 0));
end component;
signal regOutA, regOutB, dec1Out, dec2Out, dec3Out: STD_LOGIC_VECTOR(n-1 downto 0);
--END COMPONENT:
--PORT MAPPING
begin
dec1: three_to_eight_decoder port map (REA, Read_address_A, dec1Out);
dec2: three_to_eight_decoder port map (REB, Read_address_B, dec2Out);
dec3: three_to_eight_decoder port map (WE, write_address, dec3Out);
inst: for i in n-1 downto 0 generate
newReg: nbitreggistercellfile port map (Data_in, dec1Out(i), dec2Out(i), dec3Out(i), clk, outA, outB);
end generate;
end Behavioral;
----------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity three_to_eight_decoder is
Port ( OE : in std_logic;
address : in std_logic_vector(2 downto 0);
O_outputs : out std_logic_vector(3 downto 0));
end three_to_eight_decoder;
architecture with_select_arch of three_to_eight_decoder is
signal decoded : std_logic_vector(3 downto 0) ;
signal choice : std_logic_vector (3 downto 0);
begin
choice(2 downto 0) <= address;
choice(3) <= OE;
with choice select
decoded <= "0001" when "1000",
"0010" when "1001",
"0100" when "1010",
"1000" when "1011",
--"00010000" when "1100",
-- "00100000" when "1101",
-- -- "01000000" when "1110",
-- "10000000" when "1111",
-- "00000000" when "0---",
"0000" when others;
O_outputs <= decoded after 14 ns;
end with_select_arch;
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity nbitreggistercellfile is
generic(n:positive:=4);
Port ( din : in STD_LOGIC_VECTOR (n-1 downto 0);
rea : in STD_LOGIC;
reb : in STD_LOGIC;
we : in STD_LOGIC;
clk : in STD_LOGIC;
outA : out STD_LOGIC_VECTOR (n-1 downto 0);
outB : out STD_LOGIC_VECTOR (n-1 downto 0));
end nbitreggistercellfile;
architecture Behavioral of nbitreggistercellfile is
component registercellfile
Port ( din : in STD_LOGIC;
rea : in STD_LOGIC;
reb : in STD_LOGIC;
we : in STD_LOGIC;
clk : in STD_LOGIC;
oa : out STD_LOGIC;
ob : out STD_LOGIC);
end component;
begin
inst:for i in 0 to n-1 generate
A: registercellfile port map(din(i),REa,reb,we,clk,outA(i),outB(i));
end generate;
end Behavioral;
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity registercellfile is
Port ( din : in STD_LOGIC;
rea : in STD_LOGIC;
reb : in STD_LOGIC;
we : in STD_LOGIC;
clk : in STD_LOGIC;
oa : out STD_LOGIC;
ob : out STD_LOGIC);
end registercellfile;
architecture Behavioral of registercellfile is
component D_flipflop
port (d, clk, reset, preset : in std_logic;
q,qnot: out std_logic);
end component;
component twoinputmultiplexer
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : in STD_LOGIC;
output : out STD_LOGIC);
end component;
component tri_buff
Port ( Input : in std_logic;
enable : in std_logic;
Output : out std_logic);
end component;
signal feedback,toreg,notconnected:std_logic;
begin
mux: twoinputmultiplexer port map(feedback,din,we,toreg);
flipflop: D_flipflop port map(toreg,clk,'0','0',feedback,notconnected);
selectbuffer1: tri_buff port map(feedback,rea,oa);
selectbuffer2: tri_buff port map(feedback,reb,ob);
end Behavioral;
---------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- ENTITY
entity tri_buff is
Port ( Input : in std_logic;
enable : in std_logic;
Output : out std_logic);
end tri_buff;
-- ARCHITECTURE
architecture Behavioral of tri_buff is
begin
-- PROCESS
process(input, enable)
begin
-- IF statement
if enable = '1' then
output <= input;
else
output <= 'Z' ;
end if;
end process;
end Behavioral;
----------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DATA_PATH is
generic(n:positive:=4);
Port ( Input : in STD_LOGIC_VECTOR (3 downto 0);
S : in STD_LOGIC;
Write_address : in STD_LOGIC_VECTOR (2 downto 0);
Write_enable : in STD_LOGIC;
Read_address_A : in STD_LOGIC_VECTOR (2 downto 0);
Read_Enable_A : in STD_LOGIC;
Read_address_B : in STD_LOGIC_VECTOR (2 downto 0);
Read_Enable_B : in STD_LOGIC;
Function_arith_or_logic : in STD_LOGIC_VECTOR (2 downto 0);
G : in STD_LOGIC_VECTOR (2 downto 0);
Status : out STD_LOGIC;
en : in STD_LOGIC;
clk : in STD_LOGIC;
Output : inout STD_LOGIC_VECTOR (3 downto 0));
end DATA_PATH;
architecture Behavioral of DATA_PATH is
component nbittwoinputmux
generic(n:positive:=4);
Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0);
InB : in STD_LOGIC_VECTOR (n-1 downto 0);
Control : in STD_LOGIC;
Output : out STD_LOGIC_VECTOR (n-1 downto 0));
end component;
component eightXnbitregisterfile
generic(n:positive:=4);
Port ( Data_in : in STD_LOGIC_VECTOR (n-1 downto 0);
Read_address_A : in STD_LOGIC_VECTOR (2 downto 0);
Read_address_B : in STD_LOGIC_VECTOR (2 downto 0);
write_address : in STD_LOGIC_VECTOR (2 downto 0);
REA : in STD_LOGIC;
REB : in STD_LOGIC;
WE : in STD_LOGIC;
clk : in STD_LOGIC;
outA : out STD_LOGIC_VECTOR (n-1 downto 0);
outB : out STD_LOGIC_VECTOR (n-1 downto 0));
end component;
component four_bit_alu
Port ( InA : in std_logic_vector(3 downto 0);
InB : in std_logic_vector(3 downto 0);
F : in std_logic_vector(2 downto 0);
Output : out std_logic_vector(3 downto 0);
C_out : out std_logic);
end component;
component four_bit_shifter
Port ( Data_In : in std_logic_vector(3 downto 0);
G : in std_logic_vector(2 downto 0);
Output : out std_logic_vector(3 downto 0));
end component;
component fourInputOr
Port ( INA : in STD_LOGIC;
INB : in STD_LOGIC;
INC : in STD_LOGIC;
IND : in STD_LOGIC;
OUTPUT : out STD_LOGIC);
end component;
component nbitregloadhold
generic(n:positive:=4);
Port ( Dinputs : in STD_LOGIC_VECTOR (n-1 downto 0);
loadhold : in STD_LOGIC;
CLK : in STD_LOGIC;
reset : in STD_LOGIC;
preset : in STD_LOGIC;
qoutputs : inout STD_LOGIC_VECTOR (n-1 downto 0));
end component;
signal frommuxtoregfile,fromregfiletoaluA,fromregfiletoaluB,toshifter,fromshiftertomux:std_logic_vector(n-1 downto 0);
signal alucarryoutnotconnected:std_logic;
begin
A: nbittwoinputmux port map(fromshiftertomux,Input,S,frommuxtoregfile);
B: eightXnbitregisterfile port map(frommuxtoregfile,Read_address_A,Read_address_B,Write_address,Read_Enable_A,Read_Enable_B,Write_enable,clk,fromregfiletoaluA,fromregfiletoaluB);
C: four_bit_alu port map(fromregfiletoaluA,fromregfiletoaluB,Function_arith_or_logic,toshifter,alucarryoutnotconnected);
D: four_bit_shifter port map(toshifter,G,fromshiftertomux);
E: fourInputOr port map(fromshiftertomux(0),fromshiftertomux(1),fromshiftertomux(2),fromshiftertomux(3),Status);
F: nbitregloadhold port map(fromshiftertomux,en,clk,'0','0',Output);
end Behavioral;
The video explains how to manipulate the ROM memory to write the ones shifter
ROM MEMORY ONES COUNTER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
----------------------------------------------------
-- Top level design
----------------------------------------------------
entity ROM_memory is
Port ( address: in STD_LOGIC_VECTOR(3 downto 0);
condition_select: out STD_LOGIC_VECTOR(1 downto 0);
Functions: out STD_LOGIC_VECTOR(1 downto 0);
d_out: out STD_LOGIC_VECTOR(19 downto 0);
done : out STD_LOGIC;
Branch_ADDRESS_M : out STD_LOGIC_VECTOR(3 downto 0));
end ROM_memory;
----------------------------------------------------
-- Internal Architecture
----------------------------------------------------
architecture Behavioral of ROM_memory is
signal delayVal: STD_LOGIC_VECTOR(19 downto 0);
begin
-- Use a with-select statement to light up relevant LEDs
with address select
delayVal <= "0---0---0---0------0" when "0000",
"10001---0---0------0" when "0001",
"00101011101110100000" when "0010",
"000110101----1000000" when "0011",
"00111000100110010000" when "0100",
"00101010101111010000" when "0101",
"00001000100010011100" when "0110",
"0---0010101010010001" when "0111",
"00000000000000000000" when others;
d_out <= delayVal after 14 ns;
with address select
Functions <= "01" when "0000",
"00" when "0001",
"00" when "0010",
"00" when "0011",
"00" when "0100",
"00" when "0101",
"11" when "0110",
"10" when "0111",
"00" when others;
with address select
condition_select <= "01" when "0000",
"--" when "0001",
"--" when "0010",
"--" when "0011",
"--" when "0100",
"--" when "0101",
"10" when "0110",
"00" when "0111",
"00" when others;
with address select
done <= '0' when "0000",
'0' when "0001",
'0' when "0010",
'0' when "0011",
'0' when "0100",
'0' when "0101",
'0' when "0110",
'1' when "0111",
'0' when others;
with address select
Branch_ADDRESS_M <= "----" when "0000",
"----" when "0001",
"----" when "0010",
"----" when "0011",
"----" when "0100",
"----" when "0101",
"0100" when "0110",
"0000" when "0111",
"----" when others;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--- ones shifter
entity ROM_memory is
Port ( address: in STD_LOGIC_VECTOR(3 downto 0);
condition_select: out STD_LOGIC_VECTOR(1 downto 0);
Functions: out STD_LOGIC_VECTOR(1 downto 0);
d_out: out STD_LOGIC_VECTOR(19 downto 0);
done : out STD_LOGIC;
Branch_ADDRESS_M : out STD_LOGIC_VECTOR(3 downto 0));
end ROM_memory;
-- Internal Architecture
architecture Behavioral of ROM_memory is
signal delayVal: STD_LOGIC_VECTOR(19 downto 0);
--------ALU operation------------------------------
-- 000 Complement A
-- 001 And
-- 010 XOR
-- 011 or
-- 100 Increment A
-- 101 Add A+B
-- 110 Decrement A
-- 111 Subtract A-B
--------Shifter operation------------------------------
-- 000 pass
-- 001 rotate left
-- 010 shift left input 0
-- 011 shift left input 1
-- 100 pass
-- 101 rotate right
-- 110 shift right input 0
-- 111 shift right input 1
begin
with address select --Input enable 1bit,address where to write 3bits,write address enable 1bit, read address A 3bits,enableaddress A 1bit,read address B 3bits,enable address B 1bit, ALU operation 3bits, shift rotate 3 bits,output enable 1 bit
delayVal <= "0---0---0---0------0" when "0000",
"10001000100010010000" when "0001", --input a 0 the state repeats enter a 2
"00001000100011100000" when "0010", --decrement A 2-1=1 register 0=1
"00011001100001000001" when "0011",--0001 increment A by 1 0001 (incremented a and shows straight away in the output)
"00011001100110010101" when "0100",--0010 shift left input a 0 0010
"00011001100110010101" when "0101",--0100 shift left input a 0 0100
"00011001100110010101" when "0110",--1000 shift left input a 0 1000
"00011001100110010001" when "0111",--1000 1000
"00011001100110011101" when "1000",--0100 shift right input a 0 0100
"00011001100110011101" when "1001",--0010 shift right input a 0 0010
"00011001100111110000" when "1010",--subtract a -b--- 2-2=0 to make sure that address 1 returns to 0 in address 0011
"00001000100111010000" when "1011",--repeat x times ---- a+b 1+0 =1 (we do this step just because we want to check if the condition data is = to 0 repeat another time if necessary)
"00000000100010010000" when "1100",--back to state 0 a and b pass the same number (we do this step because we want to return to address 0 and previous step retur to address 2!)
"00000000000000000000" when others;
d_out <= delayVal after 14 ns;
--FUNCTION---VALUE-----COUNTER------------------------------------------
--------------------LOad is1 count is 0
----CA---- ---00---- LC=> 0 EN=>1 Count alwas go to next state n+1
----CC---- ---01---- LC=> 0 EN=>condition Next state if condition is true
----BC---- ---10---- LC=> 1 EN=>contition jump to random condition m if condition is true otherwise remain there in n
----CBC--- ---11---- LC=> condition EN=>1 Jum to another state if true otherwise continue n+1 state
-- DECIDE WHICH BRANCH FUNCTION TO USE
with address select
Functions <= "01" when "0000",
"01" when "0001",
"00" when "0010",
"00" when "0011",
"00" when "0100",
"00" when "0101",
"00" when "0110",
"00" when "0111",
"00" when "1000",
"00" when "1001",
"00" when "1010",
"11" when "1011",
"10" when "1100",
"00" when others;
--CONDITION---VALUE--
--------------------
----'1'---- ---00---- Condition alwas true continue
----Start---- ---01---- Start--- the condition is true when is 1
----Datanot zero ---10---- If calculation are not finish loop to other states
----not used--- ---11----
--DECIDE WHICH STATE TO GO IN WITH
with address select
condition_select <= "01" when "0000",
"10" when "0001",--if no value is entered then data =0 so condition is not true, if a value is entered then data not zero condition is true
"--" when "0010",
"--" when "0011",
"--" when "0100",
"--" when "0101",
"00" when "0110",
"00" when "0111",
"00" when "1000",
"00" when "1001",
"00" when "1010",
"10" when "1011",
"00" when "1100",
"00" when others;
-- IS PROGRAM DONE?
with address select
done <= '0' when "0000",
'0' when "0001",
'0' when "0010",
'0' when "0011",
'0' when "0100",
'0' when "0101",
'0' when "0110",
'0' when "0111",
'0' when "1000",
'0' when "1001",
'0' when "1010",
'0' when "1011",
'1' when "1100",
'0' when others;
-- SELECT NEXT ADDRESS IF BRANCHING
with address select
Branch_ADDRESS_M <= "----" when "0000",
"----" when "0001",
"----" when "0010",
"----" when "0011",
"----" when "0100",
"----" when "0101",
"----" when "0110",
"----" when "0111",
"----" when "1000",
"----" when "1001",
"----" when "1010",
"0010" when "1011",
"0000" when "1100",
"----" when others;
end Behavioral;
#16I/Os_2 on off switches
NET "start" LOC = "p88" ;
NET "asynchronousreset" LOC = "p87" ;
#NET "alt" LOC = "p86" ;
NET "clk" LOC = "P58" ;
#8I/Os_2 Push switches
NET "datain[0]" LOC = "p94" ;
NET "datain[1]" LOC = "p93" ;
NET "datain[2]" LOC = "p92" ;
NET "datain[3]" LOC = "p91" ;
#16I/Os_1 LEDS
NET "dataout[0]" LOC = "p126" ;
NET "dataout[1]" LOC = "p125" ;
NET "dataout[2]" LOC = "p124" ;
NET "dataout[3]" LOC = "p123" ;
NET "done" LOC = "p52" ;
No comments:
Post a Comment