This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.
The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:
The complete video tutorial at:
https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4
Lab Sheets:
http://viahold.com/y37
Lab guide
http://cogismith.com/1OwP
Final design files download:
http://quitoart.blogspot.co.uk/2017/02/microcontroller-structural-design-vhdl.html
The design in this lab covers the basics of microcontrolller structural design
Intended Controlled datapath design design:
Datapath and controller internals:
Parts working on now:
Decoder read only memory code
The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:
The complete video tutorial at:
https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4
Lab Sheets:
http://viahold.com/y37
Lab guide
http://cogismith.com/1OwP
Final design files download:
http://quitoart.blogspot.co.uk/2017/02/microcontroller-structural-design-vhdl.html
The design in this lab covers the basics of microcontrolller structural design
Intended Controlled datapath design design:
Datapath and controller internals:
Parts working on now:
This is another components which will be used to construct the controlled datapath. Refer to the lab sheets:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decRom2 is
Port ( address: in STD_LOGIC_VECTOR(3 downto 0);
condition_select: out STD_LOGIC_VECTOR(1 downto 0);
Functions: out STD_LOGIC_VECTOR(1 downto 0);
d_out: out STD_LOGIC_VECTOR(19 downto 0);
done : out STD_LOGIC;
Branch_ADDRESS_M : out STD_LOGIC_VECTOR(3 downto 0));
end decRom2;
-- Internal Architecture
architecture Behavioral of decRom2 is
signal delayVal: STD_LOGIC_VECTOR(19 downto 0);
begin
with address select --Input enable 1bit,address where to write 3bits,write address enable 1bit, read address A 3bits,enableaddress A 1bit,read address B 3bits,enable address B 1bit, ALU operation 3bits, shift rotate 3 bits,output enable 1 bit
delayVal <= "00000000000000000000" when "0000",
"10001000000000000000" when "0001", --Reads a value from the input
"00011000100010100000" when "0010",
"10101000000000000000" when "0011",
"00011001101011010000" when "0100",
"00001000100001100000" when "0101",
"00000001100110010001" when "0110",
"00000000000000000000" when others;
d_out <= delayVal after 14 ns;
--FUNCTION---VALUE-----COUNTER------------------------------------------
--------------------
----CA---- ---00---- LC=> 0 EN=>1 Count alwas go to next state n+1
----CC---- ---01---- LC=> 0 EN=>condition Next state if condition is true
----BC---- ---10---- LC=> 1 EN=>contition jump to random condition m if condition is true otherwise remain there in n
----CBC--- ---11---- LC=> condition EN=>1 Jum to another state if true otherwise continue n+1 state
-- DECIDE WHICH BRANCH FUNCTION TO USE
with address select
Functions <= "01" when "0000",
"00" when "0001",
"00" when "0010",
"00" when "0011",
"00" when "0100",
"11" when "0101",
"10" when "0110",
"01" when others;
--CONDITION---VALUE--
--------------------
----'1'---- ---00---- Condition alwas true continue
----Start---- ---01---- Start
----Datanot zero ---10---- If calculation are not finish loop to other states
----not used--- ---11----
--DECIDE WHICH STATE TO GO IN WITH
with address select
condition_select <= "01" when "0000",
"00" when "0001",
"00" when "0010",
"00" when "0011",
"00" when "0100",
"10" when "0101",
"00" when "0110",
"00" when others;
-- IS PROGRAM DONE?
with address select
done <= '0' when "0000",
'0' when "0001",
'0' when "0010",
'0' when "0011",
'0' when "0100",
'0' when "0101",
'1' when "0110",
'0' when others;
-- SELECT NEXT ADDRESS IF BRANCHING
with address select
Branch_ADDRESS_M <= "0000" when "0000",
"0000" when "0001",
"0000" when "0010",
"0000" when "0011",
"0000" when "0100",
"0011" when "0101",
"0000" when "0110",
"0000" when others;
end Behavioral;
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