electronics blog: VHDL Controller - Structural design microprocessor design in circuit ISE Xilinx CODE

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

Lab Sheets:

http://viahold.com/y37

Lab guide, Data path and control words, Controller and next state logic to manipulate the datapath:

https://yadi.sk/d/Xe62M3Ds3MoVMD

Final design files download:

http://quitoart.blogspot.co.uk/2017/02/microcontroller-structural-design-vhdl.html

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Final Controlled datapath design:

Datapath and controller internals:

--------------------------------------------------------------

CONTROL WORDS USED IN THE DATAPATH (ONES COUNTER) refer to the learning material

Lab guide, Data path and control words, Controller and next state logic to manipulate the datapath:

https://yadi.sk/d/Xe62M3Ds3MoVMD

--------------------------------------------------------------

Controller video

Code

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 use IEEE.STD_LOGIC_ARITH.ALL;  
 use IEEE.STD_LOGIC_UNSIGNED.ALL;  
 entity CONTROLLER is  
   Port ( start : in STD_LOGIC;  
       datanotzero : in STD_LOGIC;  
                 alt :in std_logic;  
       clk : in STD_LOGIC;  
       asynchronousreset : in STD_LOGIC;  
       datapathcontrol : out STD_LOGIC_VECTOR (19 downto 0);  
       done : out STD_LOGIC);  
 end CONTROLLER;  
 architecture Behavioral of CONTROLLER is  
 component fourinputmux   
 port (a : in std_logic;  
    b : in std_logic;  
    c : in std_logic;  
    d : in std_logic;  
    control : in std_logic_vector(1 downto 0);  
    output : out std_logic  
    );  
 end component;  
 component functiondecodelogic   
    Port (Condition : in STD_LOGIC;  
                     Functions : in STD_LOGIC_VECTOR (1 downto 0);  
                     Load_Count_OUT : out STD_LOGIC;  
                     Enable_OUT: out STD_LOGIC);  
 end component;  
 component nbitsynchronouscounterwithparallelload   
   Port ( dinputs : in STD_LOGIC_VECTOR (3 downto 0);  
       loadcount : in STD_LOGIC;  
       countenable : in STD_LOGIC;  
       clk : in STD_LOGIC;  
       reset : in STD_LOGIC;  
       qoutputs : inout STD_LOGIC_VECTOR (3 downto 0));  
 end component;  
 component decRom2  
      Port (  address: in STD_LOGIC_VECTOR(3 downto 0);  
                  condition_select: out STD_LOGIC_VECTOR(1 downto 0);  
                     Functions: out STD_LOGIC_VECTOR(1 downto 0);  
              d_out: out STD_LOGIC_VECTOR(19 downto 0);  
                     done : out STD_LOGIC;  
                     Branch_ADDRESS_M : out STD_LOGIC_VECTOR(3 downto 0));  
 end component;  
 signal fromromconditionselect,fromromtofunction:std_logic_vector(1 downto 0);  
 signal branchaddress,torom:std_logic_vector(3 downto 0);  
 signal tofuctiondecode,toloadcount,toenable:std_logic;  
 begin  
 A: fourinputmux port map('1',start,datanotzero,alt,fromromconditionselect,tofuctiondecode);  
 B: functiondecodelogic port map(tofuctiondecode,fromromtofunction,toloadcount,toenable);  
 C: nbitsynchronouscounterwithparallelload port map(branchaddress,toloadcount,toenable,clk,asynchronousreset,torom);   
 D: decRom2 port map(torom,fromromconditionselect,fromromtofunction,datapathcontrol,done,branchaddress);  
 end Behavioral;

Component 4 input multiplexer (code in the video description)