VHDL Datapath - Structural design microprocessor structural design in circuit ISE Xilinx CODE

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

Lab Sheets:

http://viahold.com/y37

Lab guide, Data path and control words, Controller and next state logic to manipulate the datapath:

https://yadi.sk/d/Xe62M3Ds3MoVMD

Final design files download:

http://quitoart.blogspot.co.uk/2017/02/microcontroller-structural-design-vhdl.html

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Final Controlled datapath design:

Datapath and controller internals:

       

Parts working on now:

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CONTROL WORDS USED IN THE DATAPATH (ONES COUNTER) refer to the learning material

Lab guide, Data path and control words, Controller and next state logic to manipulate the datapath:

https://yadi.sk/d/Xe62M3Ds3MoVMD

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                                       Datapath video                  

CODE datapath

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 use IEEE.STD_LOGIC_ARITH.ALL;  
 use IEEE.STD_LOGIC_UNSIGNED.ALL;  
 entity DATA_PATH is  
 generic(n:positive:=4);  
   Port ( Input : in STD_LOGIC_VECTOR (3 downto 0);  
       S : in STD_LOGIC;  
       Write_address : in STD_LOGIC_VECTOR (2 downto 0);  
       Write_enable : in STD_LOGIC;  
       Read_address_A : in STD_LOGIC_VECTOR (2 downto 0);  
       Read_Enable_A : in STD_LOGIC;  
       Read_address_B : in STD_LOGIC_VECTOR (2 downto 0);  
       Read_Enable_B : in STD_LOGIC;  
       Function_arith_or_logic : in STD_LOGIC_VECTOR (2 downto 0);  
       G : in STD_LOGIC_VECTOR (2 downto 0);  
       Status : out STD_LOGIC;  
       en : in STD_LOGIC;  
       clk : in STD_LOGIC;  
       Output : inout STD_LOGIC_VECTOR (3 downto 0));  
 end DATA_PATH;  
 architecture Behavioral of DATA_PATH is  
 component nbittwoinputmux   
 generic(n:positive:=4);  
   Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0);  
       InB : in STD_LOGIC_VECTOR (n-1 downto 0);  
       Control : in STD_LOGIC;  
       Output : out STD_LOGIC_VECTOR (n-1 downto 0));  
 end component;  
 component eightXnbitregisterfile   
 generic(n:positive:=4);  
   Port ( Data_in : in STD_LOGIC_VECTOR (n-1 downto 0);  
       Read_address_A : in STD_LOGIC_VECTOR (2 downto 0);  
       Read_address_B : in STD_LOGIC_VECTOR (2 downto 0);  
       write_address : in STD_LOGIC_VECTOR (2 downto 0);  
       REA : in STD_LOGIC;  
       REB : in STD_LOGIC;  
       WE : in STD_LOGIC;  
       clk : in STD_LOGIC;  
       outA : out STD_LOGIC_VECTOR (n-1 downto 0);  
       outB : out STD_LOGIC_VECTOR (n-1 downto 0));  
 end component;  
 component four_bit_alu   
   Port ( InA : in std_logic_vector(3 downto 0);  
       InB : in std_logic_vector(3 downto 0);  
       F : in std_logic_vector(2 downto 0);  
       Output : out std_logic_vector(3 downto 0);  
       C_out : out std_logic);  
 end component;  
 component four_bit_shifter   
   Port ( Data_In : in std_logic_vector(3 downto 0);  
       G : in std_logic_vector(2 downto 0);  
       Output : out std_logic_vector(3 downto 0));  
 end component;  
 component fourInputOr  
 Port ( INA : in STD_LOGIC;  
       INB : in STD_LOGIC;  
       INC : in STD_LOGIC;  
       IND : in STD_LOGIC;  
       OUTPUT : out STD_LOGIC);   
 end component;  
 component nbitregloadhold   
 generic(n:positive:=4);  
   Port ( Dinputs : in STD_LOGIC_VECTOR (n-1 downto 0);  
       loadhold : in STD_LOGIC;  
       CLK : in STD_LOGIC;  
       reset : in STD_LOGIC;  
       preset : in STD_LOGIC;  
       qoutputs : inout STD_LOGIC_VECTOR (n-1 downto 0));  
 end component;  
 signal frommuxtoregfile,fromregfiletoaluA,fromregfiletoaluB,toshifter,fromshiftertomux:std_logic_vector(n-1 downto 0);  
 signal alucarryoutnotconnected:std_logic;  
 begin  
 A: nbittwoinputmux      port map(fromshiftertomux,Input,S,frommuxtoregfile);  
 B: eightXnbitregisterfile   port map(frommuxtoregfile,Read_address_A,Read_address_B,Write_address,Read_Enable_A,Read_Enable_B,Write_enable,clk,fromregfiletoaluA,fromregfiletoaluB);  
 C: four_bit_alu                         port map(fromregfiletoaluA,fromregfiletoaluB,Function_arith_or_logic,toshifter,alucarryoutnotconnected);  
 D: four_bit_shifter                     port map(toshifter,G,fromshiftertomux);  
 E:     fourInputOr                    port map(fromshiftertomux(0),fromshiftertomux(1),fromshiftertomux(2),fromshiftertomux(3),Status);  
 F: nbitregloadhold                    port map(fromshiftertomux,en,clk,'0','0',Output);  
 end Behavioral;  

Component nbit 4 bit two input multiplexer (Code in the vide description)

Component 8xn eight x n bit register file (Code in the vide description)

Component 4 bit arithmetic logic unit (Component in the video description)

Component 4 bit shifter (Component in the video description)

 Component 4 input or gate code

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 -- Uncomment the following library declaration if using  
 -- arithmetic functions with Signed or Unsigned values  
 --use IEEE.NUMERIC_STD.ALL;  
 -- Uncomment the following library declaration if instantiating  
 -- any Xilinx primitives in this code.  
 --library UNISIM;  
 --use UNISIM.VComponents.all;  
 entity fourinputnorgate is  
   Port ( a : in STD_LOGIC;  
       b : in STD_LOGIC;  
       c : in STD_LOGIC;  
       d : in STD_LOGIC;  
       f : out STD_LOGIC);  
 end fourinputnorgate;  
 architecture Behavioral of fourinputnorgate is  
 begin  
 f<=(a nor b) nor (c nor d);  
 end Behavioral;  

Component nbit 4 bit register with load hold (Component in the video description)