electronics blog: VHDL 1 bit register file cell RFC register Structural design code plus test in circuit ISE Xilinx CODE

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

Parts working on now:

This is another components which will be used to construct the datapath. Refer to the lab sheets:

RFC register code

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 ----------------------------------------------------  
 -- Top level design  
 ----------------------------------------------------  
 entity RFC is  
   Port ( DIN : in STD_LOGIC;  
       REA : in STD_LOGIC;  
       REB : in STD_LOGIC;  
       WE : in STD_LOGIC;  
       CLK : in STD_LOGIC;  
       OA : out STD_LOGIC;  
       OB : out STD_LOGIC);  
 end RFC;  
 ----------------------------------------------------  
 -- Internal Architecture  
 ----------------------------------------------------  
 architecture Behavioral of RFC is  
 --COMPONENT: Two input multiplexer  
 component twoinputmultiplexer is  
   Port ( a : in STD_LOGIC;  
       b : in STD_LOGIC;  
       s : in STD_LOGIC;  
                 output : out STD_LOGIC);  
 end component;  
 --COMPONENT: d flip flop  
 component D_flipflop is  
 port (d, clk, reset, preset : in std_logic;  
           q,qnot: out std_logic);  
 end component;  
 --END COMPONENT  
 --COMPONENT: tri state buffer  
 component tri_buff is  
   Port ( Input : in std_logic;  
       enable : in std_logic;  
       Output : out std_logic);  
 end component;  
 --END COMPONENT  
 --SIGNALS:  
 signal feedback, muxToFF, ffOut, dummy: STD_LOGIC;  
 --Value stored in the flip flop is Din when WE=1 or the current value of Q otherwise  
 begin  
      newMux: twoinputmultiplexer port map(ffOut, DIN, WE, muxToFF);  
      newFF: D_flipflop port map(muxToFF, CLK, '0', '0', ffOut, dummy);  
      bufferOne: tri_buff port map(ffOut, REA, OA);  
      bufferTwo: tri_buff port map(ffOut, REB, OB);  
 end Behavioral;

Component 2 input multiplexer code