VHDL 64x8 Static RAM code plus test in circuit ISE Xilinx CODE

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP



The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

Parts working on now:

This is another components which will be used to construct the datapath. Refer to the lab sheets:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 use IEEE.STD_LOGIC_ARITH.ALL;  
 use IEEE.STD_LOGIC_UNSIGNED.ALL;  
 -- Uncomment the following library declaration if using  
 -- arithmetic functions with Signed or Unsigned values  
 --use IEEE.NUMERIC_STD.ALL;  
 -- Uncomment the following library declaration if instantiating  
 -- any Xilinx primitives in this code.  
 --library UNISIM;  
 --use UNISIM.VComponents.all;  
 entity A_64x8_bit_Static_ram is  
       Generic (n : positive:=8);  
   Port ( Address : in STD_LOGIC_VECTOR (n-3 downto 0);  
       Read_write_bar : in STD_LOGIC;  
       Chip_select : in STD_LOGIC;  
       Data_inout : inout STD_LOGIC_VECTOR (n-1 downto 0));  
 end A_64x8_bit_static_ram;  
 architecture Behavioral of A_64x8_bit_Static_ram is  
 component A_64x4_bit_static_ram    
  Generic (n : positive:=8);                                     
             Port ( Address : in STD_LOGIC_VECTOR (n-3 downto 0);  
                 Read_write_bar : in STD_LOGIC;  
                 Chip_select : in STD_LOGIC;  
                 Data_inout : inout STD_LOGIC_VECTOR (n-5 downto 0));  
 end component;  
 begin  
 FIRST_RAM:      A_64x4_bit_static_ram port map (Address,     Read_write_bar,     Chip_select,     Data_inout(7 downto 4 ));   -- gets the LSB DATA out  
 SECOND_RAM: A_64x4_bit_static_ram port map (Address,     Read_write_bar, Chip_select,     Data_inout(3 downto 0 )); -- gets the MSB DATa out  
 end Behavioral;  

Component VHDL 64x4 Static RAM code plus test in circuit ISE Xilinx CODE

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