electronics blog: VHDL 64x4 Static RAM Structural design code plus test in circuit ISE Xilinx CODE

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

Parts working on now:

This is another components which will be used to construct the datapath. Refer to the lab sheets:

CODE:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 use IEEE.STD_LOGIC_ARITH.ALL;  
 use IEEE.STD_LOGIC_UNSIGNED.ALL;  
 entity A_64x4_bit_static_ram is  
       Generic (n : positive:=8);  
   Port ( Address : in STD_LOGIC_VECTOR (n-3 downto 0);  
       Read_write_bar : in STD_LOGIC;  
       Chip_select : in STD_LOGIC;   
       Data_inout : inout STD_LOGIC_VECTOR (n-5 downto 0));  
 end A_64x4_bit_static_ram;  
 architecture Behavioral of A_64x4_bit_static_ram is  
 component three_to_eight_decoder    
                     Port (        
                                    OE : in std_logic;  
                                    address : in std_logic_vector(2 downto 0);      -- 3 bits   
                                    O_outputs : out std_logic_vector(7 downto 0));      -- 8 bits   
 end component;  
 component eight_by_four_sram  
                     Port (      address : in std_logic_vector(2 downto 0);      -- 3 bits   
                                    read_notwrite : in std_logic;  
                                    chip_select : in std_logic;  
                                    data_inout : inout std_logic_vector(3 downto 0));      -- 4 bits   
 end component;  
 signal OoUt_sig : std_logic_vector(n-1 downto 0);     -- signal connects o_outputs each element to each ram  
 signal DATA_sig: std_logic_vector(n-5 downto 0);   
 begin  
 RAM_CHOICE: three_to_eight_decoder port map (     Chip_select ,      Address(5 downto 3) ,      OoUt_sig); -- 5->3 is the MSB of address lines choose which ram.  
  inst : for i in n-1 downto 0 generate   
      SRAM_N: eight_by_four_sram port map (Address(2 downto 0) ,     Read_write_bar ,      OoUt_sig(i),     DATA_sig     ); -- 8 by 8 by 4 gives 64 words  
      Data_inout <= DATA_sig;  
 end generate;       
 end Behavioral;

Component 3 to 8 decoder