VHDL 8 x nbit bit register file cell RFC register code plus test in circuit ISE Xilinx CODE

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP



The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

Parts working on now:

This is another components which will be used to construct the controlled datapath. Refer to the lab sheets:

Code 8xnbit refister file cell

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 ----------------------------------------------------  
 -- Top level design  
 ----------------------------------------------------  
 entity n8RegFile is  
      Generic(n: positive:=8);  
      Port (dataIn:      in STD_LOGIC_VECTOR(n-1 downto 0);  
            readAddA: in STD_LOGIC_VECTOR(2 downto 0);  
            readAddB: in STD_LOGIC_VECTOR(2 downto 0);  
            wrAdd:      in STD_LOGIC_VECTOR(2 downto 0);  
            REA:           in STD_LOGIC;  
            REB:           in STD_LOGIC;  
            WE:           in STD_LOGIC;  
            CLK:           in STD_LOGIC;  
            outA:      out STD_LOGIC_VECTOR(n-1 downto 0);  
            outB:      out STD_LOGIC_VECTOR(n-1 downto 0));  
 end n8RegFile;  
 ----------------------------------------------------  
 -- Internal Architecture  
 ----------------------------------------------------  
 architecture Behavioral of n8RegFile is  
 --COMPONENT: RFC register  
 component nbitRegisterCellRCF is  
 generic(n:positive:=8);  
   Port ( Din : in STD_LOGIC_VECTOR (n-1 downto 0);  
       REA : in STD_LOGIC;  
       REB : in STD_LOGIC;  
       WE : in STD_LOGIC;  
       Clock : in STD_LOGIC;  
       OA : out STD_LOGIC_VECTOR (n-1 downto 0);  
       OB : out STD_LOGIC_VECTOR (n-1 downto 0));  
 end component;  
 --END COMPONENT: RFC register  
 --COMPONENT:  
 component three_to_eight_decoder is  
   Port (      OE : in std_logic;  
                      address : in std_logic_vector(2 downto 0);  
       O_outputs : out std_logic_vector(7 downto 0));  
 end component;  
 --SIGNALS:  
 signal regOutA, regOutB, dec1Out, dec2Out, dec3Out: STD_LOGIC_VECTOR(n-1 downto 0);  
 --END COMPONENT:  
 --PORT MAPPING  
 begin  
           dec1: three_to_eight_decoder port map (REA, readAddA, dec1Out);  
           dec2: three_to_eight_decoder port map (REB, readAddB, dec2Out);  
           dec3: three_to_eight_decoder port map (WE, wrAdd, dec3Out);  
        inst: for i in n-1 downto 0 generate  
                newReg: nbitRegisterCellRCF port map (dataIn, dec1Out(i), dec2Out(i), dec3Out(i), CLK, outA, outB);  
           end generate;  
 end Behavioral;  

Component 3 to 8 decoder

Component nbit register cell file