VHDL TDM time division multiplexer seven segment display decoder rom code plus test in circuit ISE Xilinx CODE

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

Code TDM time division multiplexer

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 ----------------------------------------------------  
 -- Top level design  
 ----------------------------------------------------  
 entity TDM is  
      Generic (n: positive:= 4);  
      Port (reset: in STD_LOGIC;  
            CLK: in STD_LOGIC;  
            InA: in STD_LOGIC_VECTOR(n-1 downto 0);  
            InB: in STD_LOGIC_VECTOR(n-1 downto 0);  
            cathA: out STD_LOGIC;  
            cathB: out STD_LOGIC;  
            anOut: out STD_LOGIC_VECTOR(6 downto 0));  
 end TDM;  
 ----------------------------------------------------  
 -- Internal Architecture  
 ----------------------------------------------------  
 architecture Behavioral of TDM is  
 --COMPONENT: t flip-flop  
 component Tflipflopasynchronous  
    Port ( reset : in STD_LOGIC;  
       CLK : in STD_LOGIC;  
       q : inout STD_LOGIC;  
       qnot : inout STD_LOGIC);  
 end component;  
 --END COMPONENT: t flip flop  
 --COMPONENT: nbitTSBuffer  
 component nbittristatebuffer        
       generic ( n : positive := 4);  
   Port ( datain : in STD_LOGIC_VECTOR (n-1 downto 0);  
       enable : in STD_LOGIC;  
       output : out STD_LOGIC_VECTOR (n-1 downto 0));  
 end component;  
 --END COMPONENT: nbitTSBuffer  
 --COMPONENT: 16-7 decoder ROM  
 component decRom16x7 is  
 Port (address:      in STD_LOGIC_VECTOR(3 downto 0);  
            d_out: out STD_LOGIC_VECTOR(6 downto 0));  
 end component;  
 --END COMPONENT: 16-7 decoder ROM  
 --SIGNALS  
 signal qout, qBarOut, test: STD_LOGIC;  
 signal ts1Out, ts2Out, toROM,dummy: STD_LOGIC_VECTOR(n-1 downto 0);  
 begin  
      newFF: Tflipflopasynchronous port map(reset, CLK, qout, qBarOut);  
      cathA <= qout;  
      test <= qout;  
      cathB <= qBarOut;  
      tsOne: nbittristatebuffer port map(InA, qout, ts1Out);  
      tsTwo: nbittristatebuffer port map(InB, qBarOut, ts2Out);  
      with test select  
           toROM <= ts1Out when '1',  
                       ts2Out when '0',  
                          dummy when others;  
      newRom: decRom16x7 port map(toROM, anOut);  
 end Behavioral; 

Component T flip flop

Component nbit 4 bit tri state buffer

Component 16x7 decooder seven segment display

ROM seven segment decoder modified for multiplexing decRom16x7:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 ----------------------------------------------------  
 -- Top level design  
 ----------------------------------------------------  
 entity decRom16x7 is  
      Port (address:      in STD_LOGIC_VECTOR(3 downto 0);  
            d_out: out STD_LOGIC_VECTOR(6 downto 0));  
 end decRom16x7;  
 ----------------------------------------------------  
 -- Internal Architecture  
 ----------------------------------------------------  
 architecture Behavioral of decRom16x7 is  
      signal delayVal: STD_LOGIC_VECTOR(6 downto 0);  
      begin  
      -- Use a with-select statement to light up relevant LEDs   
      -------------------------------------------------  
      -- Encoder   
      -------------------------------------------------  
      -- HEX-to-seven-segment decoder   
      -- segment encoding   
      --   0   
      --   ---   
      -- 5 |  | 1  
      --   --- <------6  
      -- 4 |  | 2  
      --   ---   
      --   3  
           with address select  
           delayVal <= "1000000" when "0000",--0  
                               "1111001" when "0001",--1  
                               "0100100" when "0010",--2  
                               "0110000" when "0011",--3  
                               "0011001" when "0100",--4  
                               "0010010" when "0101",--5  
                               "0000010" when "0110",--6  
                               "1111000" when "0111",--7  
                               "0000000" when "1000",--8  
                               "0010000" when "1001",--9  
                               "0001000" when "1010",--a  
                               "0000011" when "1011",--b  
                               "1000110" when "1100",--c  
                               "0100001" when "1101",--d  
                               "0000110" when "1110",--e  
                               "0001110" when "1111",--f  
                               "XXXXXXX" when others;  
           d_out <= delayVal after 14 ns;  
 end Behavioral;  

TUTORIAL ON HOW TO ADD CLOCK TIMING CONSTRAINTS IN A MODULE