VHDL Function decoder logic plus test in circuit ISE Xilinx CODE

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP



The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

Parts working on now:

This is another components which will be used to construct the controlled datapath. Refer to the lab sheets:

Code for the functiond ecoder logic

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 use IEEE.STD_LOGIC_ARITH.ALL;  
 use IEEE.STD_LOGIC_UNSIGNED.ALL;  
 entity functiondecodelogic is  
   Port ( Condition : in STD_LOGIC;  
                     Functions : in STD_LOGIC_VECTOR (1 downto 0);  
                     Load_Count_OUT : out STD_LOGIC;  
                     Enable_OUT: out STD_LOGIC);  
 end functiondecodelogic;  
 architecture Behavioral of functiondecodelogic is  
 begin  
 PROCESS(Functions,Condition)IS  
      BEGIN  
           CASE Functions IS  
                WHEN "00" => -- FUNCTION is at CA : Count always  
                     Load_Count_OUT <= '0' after 7ns; -- theses two statements will make the state increment naturally  
                     Enable_OUT <= '1';  
                WHEN "01" => -- FUNCTION is at CC : Count depends on the Condition  
                Load_Count_OUT <= '0' after 7ns; -- thses two statements will make the state increment if codition is true otherwise stay on the state  
                Enable_OUT <= Condition ;  
                WHEN "10" => -- FUNCTION is at BC : branch depends on the Condition  
                     Load_Count_OUT <= '1' after 7ns; -- thses two statements will make the state change to seperate state  
                     Enable_OUT <= Condition ;  
                WHEN "11" => -- FUNCTION is at CBC : Count or Branch Conditional  
                     Load_Count_OUT <= Condition; -- inavlid input is not used  
                     Enable_OUT <= '1';       
                     WHEN OTHERS =>   
           --FUNCTION---VALUE--  
           --------------------  
           ----CA---- ---00----                 
           ----CC---- ---01----  
           ----BC---- ---10----  
           ----CBC--- ---11----  
           END CASE;  
 END PROCESS;  
 end Behavioral;