VHDL USB Serial Handler

Universal Serial Bus

The USB protocol has become pervasive and ubiquitous in the computing and electronics industries in recent years. The protocol supports a variety of data rates from low speed (10–100 kbits/s) up
to high speed devices (up to 400 Mbits/s). While in principle it is possible to create Field Programmable Gate Array (FPGA) interfaces directly to a USB bus, for anything other than the lower data rates it requires accurate voltage matching and impedance matching of the serial bus. For example, the low data rates require 2.8V (‘1’) and 0.3 V (‘0’), differentially, whereas the high speed bus requires 400 mV signals, and in both cases termination resistors are required.

In practice, therefore, it is common when working with FPGAs to use a simple interface chip that handles all the analogue interface issues and can then be connected directly to the FPGA with a
simple UART style interface. An example device is the Silicon Labs CP2101, that takes the basic USB Connector pins (Differential Data and Power and Ground) and then sets up the basic serial data
transmission pins. The block diagram of this device is given in Figure 21.

The pins on this device are relatively self explanatory and are
summarized below:

The basic operation of the serial port starts from the use of the TXD and RXD (data) lines. If the configuration is as a NULL modem with no handshaking, it is possible to simply use the transmit
(TXD) and receive (RXD) lines alone. If you wish to check that the line is clear for sending data, then
the RTS signal can be set (Request to Send), in this case Active Low, and if the line is ready, then the CTS line will go low and the data can be sent. This basic scheme is defined in such a way that
once the receiver signal goes low, that the transmitter can send at any rate, the assumption being that the receiver can handle whatever rate is provided.

The protocol can be made more capable by using the DTR line, and this notifies the other end of the link that the device is ready for receiving data communications. The DCD line is not used directly
in the link, but indicates that there is a valid communications link between the devices.

We can develop a VHDL model for such a communications link with as much complexity as we need to communicate with the hardware in the system under consideration, starting with a simple template:

LIBRARY ieee;
USE ieee.Std_logic_1164.ALL;
USE ieee.Std_logic_unsigned.ALL;
Entity serial_handler is
Port(
Clk : in std_logic;
Nrst : in std_logic;
Data_in : in std_logic;
Data_out : out std_logic;
DTR : in std_logic;
TXD : out std_logic;
RXD : in std_logic
);
End entity serial_handler;
Architecture serial_dtr of serial_handler is
Begin
p1 : process (clk)
Begin
If rising_edge(clk) then
If DTR = '0' then
Data_out <= rxd;
End if;
Txd <= data_in;
End if;
End process p1;
End architecture serial_dtr;