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This project takes readings from a one wire temperature sensor (DS18B20) and send the data through RS232 UART serial communication to a PC using hyperterminal. The code has been implemeted using Verilog and VHDL. The communication baud rate is 19200. The development board used in this project is a Waveshare development board Spartan 3 250E.
TOP MODULE TEMPERATURE AND RS232 SERIAL COMMUNICATION
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity temperature_RS232 is
port ( CLOCK_50 : in std_logic;
Q_KEY : in std_logic;
reset : in std_logic;
RX : in std_logic;
XLXN_49 : in std_logic;
RX_empty : out std_logic;
r_data : out std_logic_vector (7 downto 0);
SEG7_SEG : out std_logic_vector (7 downto 0);
SEG7_SEL : out std_logic_vector (3 downto 0);
TX : out std_logic;
TX_full : out std_logic;
DS18B20 : inout std_logic);
end temperature_RS232;
architecture BEHAVIORAL of temperature_RS232 is
signal XLXN_17 : std_logic_vector (7 downto 0);
signal XLXN_63 : std_logic;
signal XLXI_3_rd_uart_openSignal : std_logic;
component ds18b20_seg7
port ( CLOCK_50 : in std_logic;
Q_KEY : in std_logic;
DS18B20 : inout std_logic;
SEG7_SEG : out std_logic_vector (7 downto 0);
SEG7_SEL : out std_logic_vector (3 downto 0);
data_to_pc : out std_logic_vector (7 downto 0));
end component;
component uart
port ( clk : in std_logic;
reset : in std_logic;
rd_uart : in std_logic;
wr_uart : in std_logic;
rx : in std_logic;
w_data : in std_logic_vector (7 downto 0);
tx_full : out std_logic;
rx_empty : out std_logic;
tx : out std_logic;
r_data : out std_logic_vector (7 downto 0));
end component;
component Tflipflopasynchronous
port ( reset : in std_logic;
CLK : in std_logic;
q : inout std_logic;
qnot : inout std_logic);
end component;
begin
XLXI_1 : ds18b20_seg7
port map (CLOCK_50=>CLOCK_50,
Q_KEY=>Q_KEY,
data_to_pc(7 downto 0)=>XLXN_17(7 downto 0),
SEG7_SEG(7 downto 0)=>SEG7_SEG(7 downto 0),
SEG7_SEL(3 downto 0)=>SEG7_SEL(3 downto 0),
DS18B20=>DS18B20);
XLXI_3 : uart
port map (clk=>CLOCK_50,
rd_uart=>XLXI_3_rd_uart_openSignal,
reset=>reset,
rx=>RX,
wr_uart=>XLXN_63,
w_data(7 downto 0)=>XLXN_17(7 downto 0),
rx_empty=>RX_empty,
r_data(7 downto 0)=>r_data(7 downto 0),
tx=>TX,
tx_full=>TX_full);
XLXI_6 : Tflipflopasynchronous
port map (CLK=>CLOCK_50,
reset=>XLXN_49,
q=>XLXN_63,
qnot=>open);
end BEHAVIORAL;
TEMPERATURE TOP MODULE
module ds18b20_seg7(
input CLOCK_50,
input Q_KEY,
inout DS18B20,
output [7:0] SEG7_SEG,
output [3:0] SEG7_SEL,
output [7:0] data_to_pc
);
wire [15:0] t_buf;
ds18b20_drive ds18b20_u0(
.clk(CLOCK_50),
.rst_n(Q_KEY),
.one_wire(DS18B20),
.temperature(t_buf)
);
seg_dynamic_drive seg7_u0(
.clk (CLOCK_50),
.data ({t_buf[11:8],t_buf[7:4],t_buf[3:0],4'h0}),
.dp (4'b1011),
.SEG (SEG7_SEG),
.SEG_S (SEG7_SEL),
.data_to_pc (data_to_pc)
);
endmodule
module ds18b20_drive(
input clk,
input rst_n,
inout one_wire,
output [15:0] temperature );
reg [5:0] cnt;
always @ (posedge clk, negedge rst_n)
if (!rst_n)
cnt <= 0;
else
if (cnt == 49)
cnt <= 0;
else
cnt <= cnt + 1'b1;
reg clk_1us;
always @ (posedge clk, negedge rst_n)
if (!rst_n)
clk_1us <= 0;
else
if (cnt <= 24)
clk_1us <= 0;
else
clk_1us <= 1;
reg [19:0] cnt_1us;
reg cnt_1us_clear;
always @ (posedge clk_1us)
if (cnt_1us_clear)
cnt_1us <= 0;
else
cnt_1us <= cnt_1us + 1'b1;
parameter S00 = 5'h00;
parameter S0 = 5'h01;
parameter S1 = 5'h03;
parameter S2 = 5'h02;
parameter S3 = 5'h06;
parameter S4 = 5'h07;
parameter S5 = 5'h05;
parameter S6 = 5'h04;
parameter S7 = 5'h0C;
parameter WRITE0 = 5'h0D;
parameter WRITE1 = 5'h0F;
parameter WRITE00 = 5'h0E;
parameter WRITE01 = 5'h0A;
parameter READ0 = 5'h0B;
parameter READ1 = 5'h09;
parameter READ2 = 5'h08;
parameter READ3 = 5'h18;
reg [4:0] state;
reg one_wire_buf;
reg [15:0] temperature_buf;
reg [5:0] step;
reg [3:0] bit_valid;
always @(posedge clk_1us, negedge rst_n)
begin
if (!rst_n)
begin
one_wire_buf <= 1'bZ;
step <= 0;
state <= S00;
end
else
begin
case (state)
S00 : begin //0000 0000 0001 1111 16 bit for
temperature_buf <= 16'h001F;
state <= S0;
end
S0 : begin
cnt_1us_clear <= 1;
one_wire_buf <= 0;
state <= S1;
end
S1 : begin
cnt_1us_clear <= 0;
if (cnt_1us == 500)
begin
cnt_1us_clear <= 1;
one_wire_buf <= 1'bZ;
state <= S2;
end
end
S2 : begin
cnt_1us_clear <= 0;
if (cnt_1us == 100)
begin
cnt_1us_clear <= 1;
state <= S3;
end
end
S3 : if (~one_wire)
state <= S4;
else if (one_wire)
state <= S0;
S4 : begin
cnt_1us_clear <= 0;
if (cnt_1us == 400)
begin
cnt_1us_clear <= 1;
state <= S5;
end
end
S5 : begin
if (step == 0)
begin
step <= step + 1'b1;
state <= WRITE0;
end
else if (step == 1)
begin
step <= step + 1'b1;
state <= WRITE0;
end
else if (step == 2)
begin
one_wire_buf <= 0;
step <= step + 1'b1;
state <= WRITE01;
end
else if (step == 3)
begin
one_wire_buf <= 0;
step <= step + 1'b1;
state <= WRITE01;
end
else if (step == 4)
begin
step <= step + 1'b1;
state <= WRITE0;
end
else if (step == 5)
begin
step <= step + 1'b1;
state <= WRITE0;
end
else if (step == 6)
begin
one_wire_buf <= 0;
step <= step + 1'b1;
state <= WRITE01;
end
else if (step == 7)
begin
one_wire_buf <= 0;
step <= step + 1'b1;
state <= WRITE01;
end
else if (step == 8)
begin
step <= step + 1'b1;
state <= WRITE0;
end
else if (step == 9)
begin
step <= step + 1'b1;
state <= WRITE0;
end
else if (step == 10)
begin
one_wire_buf <= 0;
step <= step + 1'b1;
state <= WRITE01;
end
else if (step == 11)
begin
step <= step + 1'b1;
state <= WRITE0;
end
else if (step == 12)
begin
step <= step + 1'b1;
state <= WRITE0;
end
else if (step == 13)
begin
step <= step + 1'b1;
state <= WRITE0;
end
else if (step == 14)
begin
one_wire_buf <= 0;
step <= step + 1'b1;
state <= WRITE01;
end
else if (step == 15)
begin
step <= step + 1'b1;
state <= WRITE0;
end
else if (step == 16)
begin
one_wire_buf <= 1'bZ;
step <= step + 1'b1;
state <= S6;
end
else if (step == 17)
begin
step <= step + 1'b1;
state <= WRITE0;
end
else if (step == 18)
begin
step <= step + 1'b1;
state <= WRITE0;
end
else if (step == 19)
begin
one_wire_buf <= 0;
step <= step + 1'b1;
state <= WRITE01;
end
else if (step == 20)
begin
step <= step + 1'b1;
state <= WRITE01;
one_wire_buf <= 0;
end
else if (step == 21)
begin
step <= step + 1'b1;
state <= WRITE0;
end
else if (step == 22)
begin
step <= step + 1'b1;
state <= WRITE0;
end
else if (step == 23)
begin
one_wire_buf <= 0;
step <= step + 1'b1;
state <= WRITE01;
end
else if (step == 24)
begin
one_wire_buf <= 0;
step <= step + 1'b1;
state <= WRITE01;
end
else if (step == 25)
begin
step <= step + 1'b1;
state <= WRITE0;
end
else if (step == 26)
begin
one_wire_buf <= 0;
step <= step + 1'b1;
state <= WRITE01;
end
else if (step == 27)
begin
one_wire_buf <= 0;
step <= step + 1'b1;
state <= WRITE01;
end
else if (step == 28)
begin
one_wire_buf <= 0;
step <= step + 1'b1;
state <= WRITE01;
end
else if (step == 29)
begin
one_wire_buf <= 0;
step <= step + 1'b1;
state <= WRITE01;
end
else if (step == 30)
begin
one_wire_buf <= 0;
step <= step + 1'b1;
state <= WRITE01;
end
else if (step == 31)
begin
step <= step + 1'b1;
state <= WRITE0;
end
else if (step == 32)
begin
one_wire_buf <= 0;
step <= step + 1'b1;
state <= WRITE01;
end
else if (step == 33)
begin
step <= step + 1'b1;
state <= S7;
end
end
S6 : begin
cnt_1us_clear <= 0;
if (cnt_1us == 750000 | one_wire)
begin
cnt_1us_clear <= 1;
state <= S0;
end
end
S7 : begin
if (step == 34)
begin
bit_valid <= 0;
one_wire_buf <= 0;
step <= step + 1'b1;
state <= READ0;
end
else if (step == 35)
begin
bit_valid <= bit_valid + 1'b1;
one_wire_buf <= 0;
step <= step + 1'b1;
state <= READ0;
end
else if (step == 36)
begin
bit_valid <= bit_valid + 1'b1;
one_wire_buf <= 0;
step <= step + 1'b1;
state <= READ0;
end
else if (step == 37)
begin
bit_valid <= bit_valid + 1'b1;
one_wire_buf <= 0;
step <= step + 1'b1;
state <= READ0;
end
else if (step == 38)
begin
bit_valid <= bit_valid + 1'b1;
one_wire_buf <= 0;
step <= step + 1'b1;
state <= READ0;
end
else if (step == 39)
begin
bit_valid <= bit_valid + 1'b1;
one_wire_buf <= 0;
step <= step + 1'b1;
state <= READ0;
end
else if (step == 40)
begin
bit_valid <= bit_valid + 1'b1;
one_wire_buf <= 0;
step <= step + 1'b1;
state <= READ0;
end
else if (step == 41)
begin
bit_valid <= bit_valid + 1'b1;
one_wire_buf <= 0;
step <= step + 1'b1;
state <= READ0;
end
else if (step == 42)
begin
bit_valid <= bit_valid + 1'b1;
one_wire_buf <= 0;
step <= step + 1'b1;
state <= READ0;
end
else if (step == 43)
begin
bit_valid <= bit_valid + 1'b1;
one_wire_buf <= 0;
step <= step + 1'b1;
state <= READ0;
end
else if (step == 44)
begin
bit_valid <= bit_valid + 1'b1;
one_wire_buf <= 0;
step <= step + 1'b1;
state <= READ0;
end
else if (step == 45)
begin
bit_valid <= bit_valid + 1'b1;
one_wire_buf <= 0;
step <= step + 1'b1;
state <= READ0;
end
else if (step == 46)
begin
bit_valid <= bit_valid + 1'b1;
one_wire_buf <= 0;
step <= step + 1'b1;
state <= READ0;
end
else if (step == 47)
begin
bit_valid <= bit_valid + 1'b1;
one_wire_buf <= 0;
step <= step + 1'b1;
state <= READ0;
end
else if (step == 48)
begin
bit_valid <= bit_valid + 1'b1;
one_wire_buf <= 0;
step <= step + 1'b1;
state <= READ0;
end
else if (step == 49)
begin
bit_valid <= bit_valid + 1'b1;
one_wire_buf <= 0;
step <= step + 1'b1;
state <= READ0;
end
else if (step == 50)
begin
step <= 0;
state <= S0;
end
end
WRITE0 :
begin
cnt_1us_clear <= 0;
one_wire_buf <= 0;
if (cnt_1us == 80)
begin
cnt_1us_clear <= 1;
one_wire_buf <= 1'bZ;
state <= WRITE00;
end
end
WRITE00 :
state <= S5;
WRITE01 :
state <= WRITE1;
WRITE1 :
begin
cnt_1us_clear <= 0;
one_wire_buf <= 1'bZ;
if (cnt_1us == 80)
begin
cnt_1us_clear <= 1;
state <= S5;
end
end
READ0 : state <= READ1;
READ1 :
begin
cnt_1us_clear <= 0;
one_wire_buf <= 1'bZ;
if (cnt_1us == 10)
begin
cnt_1us_clear <= 1;
state <= READ2;
end
end
READ2 :
begin
temperature_buf[bit_valid] <= one_wire;
state <= READ3;
end
READ3 :
begin
cnt_1us_clear <= 0;
if (cnt_1us == 55)
begin
cnt_1us_clear <= 1;
state <= S7;
end
end
default : state <= S00;
endcase
end
end
assign one_wire = one_wire_buf;
wire [15:0] t_buf = temperature_buf & 16'h07FF;
assign temperature[3:0] = (t_buf[3:0] * 10) >> 4;
assign temperature[7:4] = (((t_buf[7:4] * 10) >> 4) >= 4'd10) ? (((t_buf[7:4] * 10) >> 4) - 'd10) : ((t_buf[7:4] * 10) >> 4);
assign temperature[11:8] = (((t_buf[7:4] * 10) >> 4) >= 4'd10) ? (((t_buf[11:8] * 10) >> 4) + 'd1) + 'd2 : ((t_buf[11:8] * 10) >> 4) + 'd2;
assign temperature[15:12] = temperature_buf[12] ? 1 : 0;
endmodule
SEVEN SEGMENT DISPLAY MODULE
<------6 ---="" --="" 0-display="" 1-="" 2="" 3="" 4="" 7="" b0000000="" b0000010="" b0000011="" b0000110="" b0001000="" b0001110="" b0010000="" b0010010="" b0011001="" b0100001="" b0100100="" b0110000="" b1000000="" b1000110="" b1111000="" b1111001="" default:="" display="" end="" endcase="" endmodule="" h0:="" h1:="" h2:="" h3:="" h4:="" h5:="" h6:="" h7:="" h8:="" h9:="" ha:="" hb:="" hc:="" hd:="" he:="" hf:="" not="" seg="" span="">module seg_dynamic_drive(
input clk,
input [15:0] data,
input [3:0] dp,
output reg [3:0] SEG_S,
output reg [7:0] SEG,
output reg [7:0] data_to_pc
);
//------------------------------------------
reg [16:0] cnt;
always @ (posedge clk)
cnt <= cnt + 1'b1;
reg [3:0] ASCII;
reg [3:0] HEX;
always @ (posedge clk)
begin
case(cnt[16:15])
2'b00 : HEX <= data[3:0];
2'b01 : HEX <= data[7:4];
2'b10 : HEX <= data[11:8];
2'b11 : HEX <= data[15:12];
default : ;
endcase
end
always @ (posedge clk)
begin
case(cnt[16:15])
2'b11 : ASCII<= 4'b1111;
2'b10 : ASCII <= data[7:4];
2'b01 : ASCII <= data[11:8];
2'b00 : ASCII <= data[15:12];
default : ;
endcase
end
//--------------drive SEG_S----------------------
//Get SEG_S through cnt[16:15] ,every 2.6114 mS move one time
always @ (posedge clk)
begin
case(cnt[16:15])
2'b00 : SEG_S <= 4'b0001;
2'b01 : SEG_S <= 4'b0010;
2'b10 : SEG_S <= 4'b0100;
2'b11 : SEG_S <= 4'b1000;
default : ;
endcase
end
//---------drive dp------------------
always @ (posedge clk)
begin
case(cnt[16:15])
2'b00 : SEG[7] <= dp[0];
2'b01 : SEG[7] <= dp[1];
2'b10 : SEG[7] <= dp[2];
2'b11 : SEG[7] <= dp[3];
default : ;
endcase
end
//---------------------------------------
always @ (ASCII)
begin
case(ASCII)
4'h0: data_to_pc[7:0] <= 8'b00110000;//00110000 // 0-display 1- not display
4'h1: data_to_pc[7:0] <= 8'b00110001;//00110001
4'h2: data_to_pc[7:0] <= 8'b00110010;//00110010
4'h3: data_to_pc[7:0] <= 8'b00110011;//00110011
4'h4: data_to_pc[7:0] <= 8'b00110100;//00110100
4'h5: data_to_pc[7:0] <= 8'b00110101;//00110101
4'h6: data_to_pc[7:0] <= 8'b00110110;//00110110
4'h7: data_to_pc[7:0] <= 8'b00110111;//00110111
4'h8: data_to_pc[7:0] <= 8'b00111000;//00111000
4'h9: data_to_pc[7:0] <= 8'b00111001;//00111001
4'hA: data_to_pc[7:0] <= 8'b01000001;//01000001
4'hB: data_to_pc[7:0] <= 8'b01000010;//01000010
4'hC: data_to_pc[7:0] <= 8'b01000011;//01000011
4'hD: data_to_pc[7:0] <= 8'b01000100;//01000100
4'hE: data_to_pc[7:0] <= 8'b01000101;//01000101
4'hF: data_to_pc[7:0] <= 8'b00001101;//01000110
default: ;
endcase
end
always @ (HEX)
begin
case(HEX)
4'h0: SEG[6:0] <= 7'b1000000; // 0-display 1- not display
4'h1: SEG[6:0] <= 7'b1111001;
4'h2: SEG[6:0] <= 7'b0100100;
4'h3: SEG[6:0] <= 7'b0110000;
4'h4: SEG[6:0] <= 7'b0011001;
4'h5: SEG[6:0] <= 7'b0010010;
4'h6: SEG[6:0] <= 7'b0000010;
4'h7: SEG[6:0] <= 7'b1111000;
4'h8: SEG[6:0] <= 7'b0000000;
4'h9: SEG[6:0] <= 7'b0010000;
4'hA: SEG[6:0] <= 7'b0001000;
4'hB: SEG[6:0] <= 7'b0000011;
4'hC: SEG[6:0] <= 7'b1000110;
4'hD: SEG[6:0] <= 7'b0100001;
4'hE: SEG[6:0] <= 7'b0000110;
4'hF: SEG[6:0] <= 7'b0001110;
default: ;
endcase
end
endmodule
UART TOP MODULE
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart is
generic (
-- D e f a u l t s e t t in g :
-- 1 9 2 0 0 b a u d , 8 d a t a b i t s , 1 s t o p b i t , 2 ^ 2 FIFO
DBIT : integer :=8; -- # d a t a b i t s
SB_TICK: integer:=16; -- # t i c k s f o r s t o p b i t s , 1 6 / 2 4 / 3 2
DVSR: integer:= 163; -- baud r a t e d i v i s o r
DVSR_BIT: integer:=8; -- # b i t s of DVSR
FIFO_W: integer:=2 -- # a d d r b i t s of FIFO
-- for 1 / 1 . 5 / 2 s t o p b i t s
-- DVSR = 5 0 M / ( 1 6 * b a u d r a t e )
-- # w o r d s in FIFO=2^FIFO_W
) ;
port (
clk, reset: in std_logic;
rd_uart , wr_uart : in std_logic ;
rx: in std_logic;
w_data: in std_logic_vector ( 7 downto 0 ) ;
tx_full, rx_empty: out std_logic;
r_data: out std_logic_vector ( 7 downto 0) ;
tx: out std_logic
) ;
end uart;
architecture str_arch of uart is
signal rx_done_tick: std_logic;
signal tick: std_logic ;
signal tx_fifo_out : std_logic_vector ( 7 downto 0) ;
signal rx_data_out : std_logic_vector ( 7 downto 0) ;
signal tx_empty , tx_fifo_not_empty : std_logic ;
signal tx_done_tick : std_logic ;
begin
baud_gen_unit: entity work.mod_m_counter(arch)
generic map(M=>DVSR , N=>DVSR_BIT)
port map(clk=>clk, reset=>reset ,
q=>open , max_tick=>tick) ;
uart_rx_unit: entity work.uart_rx(arch)
generic map(DBIT=>DBIT, SB_TICK=>SB_TICK)
port map(clk=>clk, reset=>reset , rx=>rx,
s_tick=>tick, rx_done_tick=>rx_done_tick,
dout=>rx_data_out) ;
fifo_rx_unit: entity work.fifo(arch)
generic map(B=>DBIT , W=>FIFO_W)
port map(clk=>clk, reset=>reset , rd=>rd_uart ,
wr=>rx_done_tick , w_data=>rx_data_out ,
empty=>rx_empty, full=>open, r_data=>r_data);
fifo_tx_unit: entity work.fifo(arch)
generic map(B=>DBIT , W=>FIFO_W)
port map(clk=>clk, reset=>reset, rd=>tx_done_tick,
wr=>wr_uart, w_data=>w_data, empty=>tx_empty,
full=>tx_full, r_data=>tx_fifo_out);
uart_tx_unit : entity work.uart_tx(arch)
generic map ( DBIT => DBIT , SB_TICK => SB_TICK )
port map(clk=>clk, reset=>reset ,
tx_start=>tx_fifo_not_empty,
s_tick=>tick, din=>tx_fifo_out,
tx_done_tick=> tx_done_tick, tx=>tx);
tx_fifo_not_empty <= not tx_empty;
end str_arch;
BAUD RATE GENERATOR
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity mod_m_counter is
generic (
N: integer := 4; -- number o f b i t s
M : integer := 10); -- m o d 4
port (
clk, reset: in std_logic;
max_tick: out std_logic;
q: out std_logic_vector ( N - 1 downto 0);
an: out std_logic_vector(3 downto 0);
sseg: out std_logic_vector ( 7 downto 0)
);
end mod_m_counter ;
architecture arch of mod_m_counter is
signal cath,off: std_logic ;
signal r_reg : unsigned ( N - 1 downto 0 ) ;
signal r_next : unsigned ( N - 1 downto 0 ) ;
begin
--enabling the fir
process (clk, reset)
begin
if (reset='1') then
r_reg <= ( others => '0' ) ;
elsif (clk'event and clk='1') then
r_reg <= r_next;
end if ;
end process ;
--n e x t - s t a t e l o g i c
r_next <= ( others => '0' ) when r_reg=(M-1) else
r_reg + 1;
-- o u t p u t l o g i c
q <= std_logic_vector(r_reg);
max_tick <= '1' when r_reg=(M-1) else '0' ;
end arch;
UART RX
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_rx is
generic (
DBIT : integer := 8 ; -- # data b i t s
SB_TICK: integer := 16 -- # t i c k s f o r stop b i t s
) ;
port (
clk , reset : in std_logic ;
rx : in std_logic ;
s_tick : in std_logic ;
rx_done_tick : out std_logic ;
dout : out std_logic_vector ( 7 downto 0)
) ;
end uart_rx ;
architecture arch of uart_rx is
type state_type is ( idle , start , data , stop ) ;
signal s_reg , s_next : unsigned ( 3 downto 0) ;
signal n_reg , n_next : unsigned ( 2 downto 0) ;
signal b_reg , b_next : std_logic_vector ( 7 downto 0) ;
signal state_reg , state_next : state_type ;
begin
-- FSMD s t a t e & data r e g is t e r s
process ( clk , reset )
begin
if reset = '1' then
state_reg <= idle ;
s_reg <= ( others => '0' ) ;
n_reg <= ( others => '0' ) ;
b_reg <= ( others => '0' ) ;
elsif ( clk'event and clk = '1' ) then
state_reg <= state_next ;
s_reg <= s_next ;
n_reg <= n_next ;
b_reg <= b_next ;
end if ;
end process ;
process ( state_reg , s_reg , n_reg , b_reg , s_tick, rx )
begin
-- n e x t - s t a t e l o g i c & data p a t h f u n c t i o n a l u n i t s / r o u t i n g
state_next <= state_reg ;
s_next <= s_reg ;
n_next <= n_reg ;
b_next <= b_reg ;
rx_done_tick <= '0' ;
case state_reg is
when idle =>
if rx = '0' then
state_next <= start ;
s_next <= ( others => '0' ) ;
end if ;
when start =>
if ( s_tick = '1') then
if s_reg = 7 then
state_next <= data ;
s_next <= ( others => '0' ) ;
n_next <= ( others => '0' ) ;
else
s_next <= s_reg + 1 ;
end if ;
end if ;
when data =>
if ( s_tick = '1') then
if s_reg = 15 then
s_next <= ( others => '0' ) ;
b_next <= rx & b_reg ( 7 downto 1) ;
if n_reg = (DBIT - 1) then
state_next <= stop ;
else
n_next <= n_reg + 1 ;
end if ;
else
s_next <= s_reg + 1;
end if ;
end if ;
when stop =>
if ( s_tick = '1') then
if s_reg=(SB_TICK - 1) then
state_next <= idle;
rx_done_tick <='1';
else
s_next <= s_reg + 1 ;
end if ;
end if ;
end case ;
end process ;
dout <= b_reg ;
end arch;
FIFO BUFFER
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all ;
entity fifo is
generic (
B: natural:=8; -- number of b i t s
W: natural:=4 -- number o f a d d r e s s b i t s
);
port (
clk, reset: in std_logic;
rd, wr: in std_logic;
w_data: in std_logic_vector ( B - 1 downto 0) ;
empty, full : out std_logic;
r_data: out std_logic_vector ( B - 1 downto 0 )
);
end fifo;
architecture arch of fifo is
type reg_file_type is array (2**W-1 downto 0) of std_logic_vector ( B - 1 downto 0) ;
signal array_reg : reg_file_type ;
signal w_ptr_reg , w_ptr_next , w_ptr_succ : std_logic_vector (W-1 downto 0 ) ;
signal r_ptr_reg , r_ptr_next , r_ptr_succ:std_logic_vector ( W - 1 downto 0) ;
signal full_reg , empty_reg , full_next , empty_next :std_logic;
signal wr_op: std_logic_vector (1 downto 0 ) ;
signal wr_en : std_logic ;
begin
-- r e g is t e r f i l e
process (clk, reset)
begin
if (reset='1' ) then
array_reg <= ( others => ( others => '0' ) ) ;
elsif (clk'event and clk='1') then
if wr_en='1' then
array_reg(to_integer(unsigned(w_ptr_reg)))
<= w_data;
end if ;
end if ;
end process ;
-- r e a d p o r t
r_data <= array_reg(to_integer(unsigned(r_ptr_reg)));
--w r i t e e n a b l e d o n l y when FIFO is not f u l l
wr_en <= wr and ( not full_reg);
--
-- f if o c o n t r o l l o g i c
-- r e g is t e r f o r r e a d and w r i t e p o in t e r s
process (clk , reset)
begin
if (reset='1') then
w_ptr_reg <= ( others => '0' ) ;
r_ptr_reg <= ( others => '0' ) ;
full_reg <= '0' ;
empty_reg <= '1' ;
elsif(clk'event and clk='1') then
w_ptr_reg <= w_ptr_next ;
r_ptr_reg <= r_ptr_next ;
full_reg <= full_next;
empty_reg <= empty_next ;
end if ;
end process ;
-- s u c c e s s i v e p o in t e r v a l u e s
w_ptr_succ <= std_logic_vector (unsigned(w_ptr_reg)+1) ;
r_ptr_succ <= std_logic_vector(unsigned(r_ptr_reg)+1);
-- n e x t - s t a t e logic f o r r e a d and w r i t e p o in t e r s
wr_op <= wr & rd;
process (w_ptr_reg, w_ptr_succ ,r_ptr_reg ,r_ptr_succ ,wr_op,empty_reg , full_reg)
begin
w_ptr_next <= w_ptr_reg;
r_ptr_next <= r_ptr_reg;
full_next <= full_reg;
empty_next <= empty_reg ;
case wr_op is
when "00" => -- no op
when "01" => -- r e a d
if (empty_reg /= '1') then -- not e m p t y
r_ptr_next <= r_ptr_succ;
full_next <= '0' ;
if (r_ptr_succ=w_ptr_reg) then
empty_next <='1';
end if ;
end if ;
when "10" => -- w r i t e
if (full_reg /= '1' ) then -- if fifo not f u l l we write values
w_ptr_next <= w_ptr_succ;
empty_next <= '0' ;
if (w_ptr_succ=r_ptr_reg) then-- otherwise stop writing because is full, write pointer and read pointer point to the same place
full_next <='1';
end if ;
end if ;
when others => -- w r i t e / r e a d ;
w_ptr_next <= w_ptr_succ ;
r_ptr_next <= r_ptr_succ ;
end case ;
end process ;
-- out p u t
full <= full_reg;
empty <= empty_reg;
end arch;
UART TX
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_tx is
generic(
DBIT : integer :=8 ; -- # data b i t s
SB_TICK: integer :=16 -- # t i c k s f o r stop b i t s
);
port (
clk, reset: in std_logic;
tx_start : in std_logic;
s_tick: in std_logic ;
din: in std_logic_vector ( 7 downto 0) ;
tx_done_tick: out std_logic;
tx: out std_logic
) ;
end uart_tx ;
architecture arch of uart_tx is
type state_type is (idle, start, data, stop);
signal state_reg, state_next : state_type;
signal s_reg , s_next : unsigned (3 downto 0) ;
signal n_reg , n_next : unsigned (2 downto 0) ;
signal b_reg , b_next : std_logic_vector (7 downto 0 ) ;
signal tx_reg , tx_next : std_logic ;
-- FSMD s t a t e C? data r e g is t e r s
begin
process (clk, reset)
begin
if reset= '1' then
state_reg <= idle;
s_reg <= ( others => '0' ) ;
n_reg <= ( others => '0' ) ;
b_reg <= ( others => '0' ) ;
tx_reg <= '1';
elsif ( clk'event and clk = '1' ) then
state_reg <= state_next;
s_reg <= s_next;
n_reg <= n_next;
b_reg <= b_next;
tx_reg <= tx_next;
end if ;
end process ;
-- n e x t - s t a t e l o g i c & data p a t h f u n c t i o n a l u n i t s / r o u t i n g
process (state_reg , s_reg ,n_reg ,b_reg, s_tick,tx_reg,tx_start,din)
begin
state_next <= state_reg;
s_next <= s_reg;
n_next <= n_reg;
b_next <= b_reg;
tx_next <= tx_reg ;
tx_done_tick <= '0' ;
case state_reg is
when idle =>
tx_next <= '1' ;
if tx_start = '1' then
state_next <= start ;
s_next <= ( others => '0' ) ;
b_next <= din ;
end if ;
when start =>
tx_next <= '0' ;
if ( s_tick = '1') then
if s_reg = 15 then
state_next <= data ;
s_next <= ( others => '0' ) ;
n_next <= ( others => '0' ) ;
else
s_next <= s_reg + 1 ;
end if ;
end if ;
when data =>
tx_next <= b_reg(0);
if ( s_tick = '1') then
if s_reg = 15 then
s_next <= ( others => '0' ) ;
b_next <= '0' & b_reg ( 7 downto 1) ;
if n_reg = ( DBIT -1) then
state_next <= stop ;
else
n_next <= n_reg + 1 ;
end if ;
else
s_next <= s_reg + 1;
end if ;
end if ;
when stop =>
tx_next <= '1' ;
if ( s_tick = '1') then
if s_reg = (SB_TICK -1) then
state_next <= idle ;
tx_done_tick <= '1';
else
s_next <= s_reg + 1;
end if ;
end if ;
end case ;
end process ;
tx <= tx_reg ;
end arch ;
T FLIFLOP
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:37:29 12/28/2014
-- Design Name:
-- Module Name: Tflipflopasynchronous - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Tflipflopasynchronous is
Port ( reset : in STD_LOGIC;
CLK : in STD_LOGIC;
q : inout STD_LOGIC;
qnot : inout STD_LOGIC);
end Tflipflopasynchronous;
architecture Behavioral of Tflipflopasynchronous is
begin
process(reset,CLK)
begin
if reset='1' then
q<='0';
qnot<='1';
else
if CLK='1' and CLK'event then
q <= not q after 7ns;
qnot <= not qnot after 7ns;
end if;
end if;
end process;
end Behavioral;
CONSTRAINTS
#8I/Os_2 (Input)
NET "reset" LOC = "p81" ;
#8I/Os_2 (Input)
#8I/Os_1
NET "rx" LOC = "p39" ;
NET "tx" LOC = "p40" ;
#8I/Os_1
NET "rx" LOC = "p54" ;
NET "tx" LOC = "p58" ;
NET "CLOCK_50" LOC = P129 ;
NET "Q_KEY" LOC = P69 ;
NET "DS18B20" LOC = "p83" ;
#NET "sw" LOC = "p82" ;
NET "SEG7_SEL[0]" LOC = "p113" ;
NET "SEG7_SEL[1]" LOC = "p117" ;
NET "SEG7_SEL[2]" LOC = "p123" ;
NET "SEG7_SEL[3]" LOC = "p125" ;
NET "SEG7_SEG[0]" LOC ="p126" ;
NET "SEG7_SEG[1]" LOC = "p124" ;
NET "SEG7_SEG[2]" LOC ="p122" ;
NET "SEG7_SEG[3]" LOC ="p116" ;
NET "SEG7_SEG[4]" LOC = "p112" ;
NET "SEG7_SEG[5]" LOC = "p105" ;
NET "SEG7_SEG[6]" LOC = "p103" ;
NET "SEG7_SEG[7]" LOC = "p97" ;
NET "DS18B20" PULLUP;
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