VHDL NRZI USB decoder encoder

NRZ coding and decoding

The NRZ encoding scheme is actually not a coding scheme at all. It simply states that a ‘0’ is transmitted as a ‘0’ and a ‘1’ is transmitted as a ‘1’. It is only worth mentioning because a designer may see the term NRZ and assume that a specific encoder or decoder was required, whereas in fact this is not the case. It is also worth noting that there are some significant disadvantages in using this simple approach. The first disadvantage, especially when compared to the Manchester coding scheme is that long sequences of ‘0’s or ‘1’s give effectively DC values when transmitted, that are susceptible to problems of noise and also make clock recovery very difficult. The other issue is that of bandwidth. Again if we compare the coding scheme to that of the Manchester example, it is obvious that the Manchester scheme requires quite a narrow bandwidth (relatively) to transmit the data, whereas the NRZ scheme may require anything from DC up to half the data rate (Nyquist frequency) and anything in between. This makes line design and filter design very much more problematic.

NRZI coding and decoding 

In the NRZI scheme, the potential problems of the NRZ scheme, particularly the long periods of DC levels are partially alleviated. In the NRZI, if the data is a ‘0’, then the data does not change, whereas if a ‘1’ occurs on the data line, then the output changes. Therefore the issue of long sequences of ‘1’s is addressed, but the potential for long sequences of ‘0’s remains. It is a simple matter to create a basic model for a NRZI encoder using the following VHDL model:

library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL; 
Entity nrzi_encoder is
Port (
CLK : in std_logic;
D : in std_logic;
Q : out std_logic
);
End entity nrzi_encoder;
Architecture basic of nrzi_encoder is
Signal qint : std_logic := '0';
Begin
p1 : process (clk)
Begin
If (d = '1') then
If ( qint = '0' ) then
Qint <= '1';
else
Qint <= '0';
End if;
End if;
End process p1;
Q <= qint;
End architecture basic;
-----------------------------------
library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL; 
Entity nrzi_decoder is
Port (
CLK : in std_logic;
D : in std_logic;
Q : out std_logic
);
End entity nrzi_decoder;
Architecture basic of nrzi_decoder is
Signal lastd : std_logic := '0';
Begin
p1 : process (clk)
Begin
If rising_edge(clk) then
If (d = lastd) then
Q <= '0';
Else
Q <= '1';
End if;
Lastd <= d;
End if;
End process p1;
End architecture basic;