MATLAB VHDL code generation 1 bit NOT GATE example High level Synthesis

function [led] = not_gate (sw)
led = false(1,1);
if sw(1) == 0
    led(1)=1;
else
    led(1)=0; 
end
end

-- -------------------------------------------------------------
-- 
-- File Name: C:\Users\Felipe\Documents\MATLAB\codegen\not_gate\hdlsrc\not_gate_fixpt.vhd
-- Created: 2017-11-14 13:36:57
-- 
-- Generated by MATLAB 9.0, MATLAB Coder 3.1 and HDL Coder 3.8
-- 
-- 
-- 
-- -------------------------------------------------------------
-- Rate and Clocking Details
-- -------------------------------------------------------------
-- Design base rate: 1
-- 
-- -------------------------------------------------------------


-- -------------------------------------------------------------
-- 
-- Module: not_gate_fixpt
-- Source Path: not_gate_fixpt
-- Hierarchy Level: 0
-- 
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY not_gate_fixpt IS
  PORT( sw                                :   IN    std_logic;
        led                               :   OUT   std_logic
        );
END not_gate_fixpt;


ARCHITECTURE rtl OF not_gate_fixpt IS

BEGIN
  --HDL code generation from MATLAB function: not_gate_fixpt
  --%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
  --                                                                          %
  --           Generated by MATLAB 9.0 and Fixed-Point Designer 5.2           %
  --                                                                          %
  --%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
  led <=  NOT sw;

END rtl;