VHDL Synchronous RAM

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
ENTITY SRAM IS
GENERIC (
M : natural := 10;
N : natural := 8
);
PORT (
clk : in std_logic;
addr : in std_logic_vector(m-1 downto 0);
wr : in std_logic;
d : in std_logic_vector (n-1 downto 0);
q : out std_logic_vector (n-1 downto 0)
);
END ENTITY SRAM;
Architecture dualport of sram is
Type sramdata is array (0 to 2**m-1) of
Std_logic_vector (n-1 downto 0);
Signal memory : sramdata;
Begin
Process (clk ) is
Begin
If rising_edge(clk) then
If wr = '0' then
Memory(to_integer(unsigned(addr))) <= d;
Else
Q <= memory(to_integer(unsigned(addr)));
End if;
End if;
End process;
End architecture dualport;