VHDL Manchester Encoder Decoder

Manchester encoding is a simple coding scheme that translates a basic bit stream into a series of transitions. It is extremely useful for ensuring that a specific bandwidth can be used for data transmission, as no matter what the sequence of the data bits, the frequency of the transmitted stream will be exactly twice the frequency of the original data. It also makes signal recovery trivial, because there is no need to attempt to extract a clock as the data can be recovered simply by looking for the edges in the data and extracting asynchronously.

library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL; 
Entity Manchester_encoder is
Port (
Clk : in std_logic;
D : in std_logic;
Q : out std_logic
);
End entity Manchester_encoder;
Architecture basic of Manchester_encoder is
Begin
Q <= D XOR CLK;
End architecture basic;
--===================================================



library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  

Entity Manchester_decoder is
Port (
Clk : in std_logic;
D : in std_logic;
Q : out std_logic
);
End 
entity Manchester_decoder;
Architecture basic of Manchester_decoder is
Signal lastd : std_logic := '0';
Begin
P1 : process (clk)
Begin
If rising_edge(clk) then
Lastd <= d;
End if;
If falling_edge(clk) then
If (lastd = '0') and (d = '1') then
Q <= '1';
Elsif (lastd = '1') and (d = '0') then
Q <= '0';
Else
Q <= 'X';
End if;
End if;
End process p1;
End architecture basic;