Sign Magnitud Adder with seven segment display
Sign Magnitud Adder
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Sign Magnitud Adder
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library ieee;
use ieee. std_logic_1164.all;
use ieee . numeric_std.all ;
entity sm_add_test is
port (
clk: in std_logic;
btn: in std_logic_vector (1 downto 0) ;
sw: in std_logic_vector ( 7 downto 0) ;
an: out std_logic_vector (3 downto 0) ;
sseg : out std_logic_vector ( 7 downto 0)
) ;
end sm_add_test;
architecture arch of sm_add_test is
signal sum, mout , oct : std_logic_vector (3 downto 0);
signal led3, led2, led1 , led0 : std_logic_vector ( 7 downto 0);
begin
--i n s t a n t i a t e a d d e r
sm_adder_unit : entity work.sign_mag_add
generic map ( N =>4)
port map(a=>sw(3 downto 0) , b=>sw(7 downto 4),
sum=>sum);
-- 3 - t o - I mux t o s e l e c t a n u m b e r t o d is p l a y
with btn select
mout <=
sw(3 downto 0) when "00" , -- a
sw(7 downto 4) when "01", -- b
sum when others;--sum
-- m a g n i t u d e d is p l a y e d on r i g h t m o s t 7 - s e g LED
oct <= '0' & mout (2 downto 0) ;
sseg_unit : entity work.hex_to_sseg
--s i g n displayed on 2 n d 7 - s e g LED
port map(hex=>oct , dp=> '0' , sseg=>led0);
led1 <= "10111111" when mout(3)='1' else -- m i d d l e b a r
"11111111";
-- o t h e r two 7 - s e g LEDs b l a n k
led2 <= "11111111" ;
led3 <= "11111111";
-- in s t a n t i a t e
disp_unit : entity work.disp_mux
port map(
clk=>clk, reset=>'0',
in0=>led0, in1=>led1, in2=>led2, in3=>led3,
an=>an, sseg=>sseg) ;
end arch;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sign_mag_add is
generic(N: integer:=4);
Port ( a : in STD_LOGIC_vector(n-1 downto 0);
b : in STD_LOGIC_vector(n-1 downto 0);
sum : out STD_LOGIC_vector(n-1 downto 0));
end sign_mag_add;
architecture Behavioral of sign_mag_add is
signal mag_a , mag_b : unsigned(N-2 downto 0 ) ;
signal mag_sum , max , min: unsigned(N-2 downto 0) ;
signal sign_a , sign_b , sign_sum: std_logic;
begin
mag_a <= unsigned (a(N-2 downto 0 )) ;
mag_b <= unsigned(b(N-2 downto 0 ) ) ;
sign_a <= a(N-1);
sign_b <= b(N-1);
--s o r t a c c o r d i n g t o m a g n i t u d e
process (mag_a ,mag_b , sign_a, sign_b)
begin
if mag_a > mag_b then
max <= mag_a;
min <= mag_b;
sign_sum <= sign_a;
else
max <= mag_b;
min <= mag_a;
sign_sum <= sign_b;
end if;
end process;
-- a d d / s u b m a g n i t u d e
mag_sum <= max + min when sign_a=sign_b
else
max - min;
--form o u t p u t
sum <= std_logic_vector(sign_sum & mag_sum);
end Behavioral;
library ieee;
use ieee. std_logic_1164.all;
entity hex_to_sseg is
port (
hex: in std_logic_vector (3 downto 0 ) ;
dp: in std_logic;
sseg: out std_logic_vector (7 downto 0 )
);
end hex_to_sseg;
architecture arch of hex_to_sseg is
begin
with hex select
--hex - t o - 7- s e g in e IZ t I e d decoding
-- Use a with-select statement to light up relevant LEDs
-------------------------------------------------
-- Encoder
-------------------------------------------------
-- HEX-to-seven-segment decoder
-- segment encoding
-- 0
-- ---
-- 5 | | 1
-- --- <------6
-- 4 | | 2
-- ---
-- 3
sseg(6 downto 0 ) <=
--6543210
"1000000" when "0000",--0
"1111001" when "0001",--1
"0100100" when "0010",--2
"0110000" when "0011",--3
"0011001" when "0100",--4
"0010010" when "0101",--5
"0000010" when "0110",--6
"1111000" when "0111",--7
"0000000" when "1000",--8
"0010000" when "1001",--9
"0001000" when "1010",--a
"0000011" when "1011",--b
"1000110" when "1100",--c
"0100001" when "1101",--d
"0000110" when "1110",--e
"0001110" when "1111",--f
"XXXXXXX" when others;
sseg(7) <= dp;
end arch;
library ieee;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity disp_mux is
port(
clk,reset: in std_logic;
in3,in2,in1,in0: in std_logic_vector(7 downto 0 ) ;
an: out std_logic_vector (3 downto 0 ) ;
sseg : out std_logic_vector ( 7 downto 0 )
);
end disp_mux ;
architecture arch of disp_mux is
--r e f r e s h i n g r a t e a r o u n d 800 Hz ( 5 0 M H z / 2 ^ 1 6 )
constant N : integer :=3;
signal q_reg , q_next : unsigned ( N-1 downto 0) ;
signal sel: std_logic_vector (1 downto 0 ) ;
--r e g i s t e r
begin
process (clk, reset)
begin
if reset='1' then
q_reg <= ( others => '0' ) ;
elsif(clk'event and clk='1') then
q_reg <= q_next;
end if ;
end process ;
--n e x t - s t a t e l o g i c f o r t h e c o u n t e r
q_next <= q_reg + 1 ;
-- 2 MSBs o f c o u n t e r t o c o n t r o l 4 - t o - I m u l t i p l e x i n g
-- and t o g e n e r a t e a c t i v e - l o w e n a b l e s i g n a l
sel <= std_logic_vector(q_reg(N-1 downto N-2)) ;
process (sel , in0, in1 , in2, in3)
begin
case sel is
when "00" =>
an <= "0001";
sseg <= in0;
when "01" =>
an <= "0010";
sseg <= in1;
when "10" =>
an <= "0100";
sseg <= in2;
when others =>
an <= "1000";
sseg <= in3;
end case;
end process;
end arch;
TUTORIAL ON HOW TO ADD CLOCK TIMING CONSTRAINTS IN A MODULE
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