VHDL Mod m counter with seven segment display implemented using a xilinx spartan 3 development board with code and files

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MOD M COUNTER

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 use IEEE.numeric_std.ALL;  
 entity mod_m_counter is  
 generic (  
 N: integer := 4; -- number o f b i t s  
 M : integer := 10); -- m o d 4  
 port (  
 clk, reset: in std_logic;  
 max_tick: out std_logic;  
 q: out std_logic_vector ( N - 1 downto 0);  
 an: out std_logic_vector(3 downto 0);  
 sseg: out std_logic_vector ( 7 downto 0)  
 );  
 end mod_m_counter ;  
 architecture arch of mod_m_counter is  
 signal cath,off: std_logic ;  
 signal r_reg : unsigned ( N - 1 downto 0 ) ;  
 signal r_next : unsigned ( N - 1 downto 0 ) ;  
 signal output : std_logic_vector (N-1 downto 0);  
 begin  
 --enabling the first cathod  
 cath<='1';  
 off<='0';  
 an(0)<=cath;  
 an(1)<=off;  
 an(2)<=off;  
 an(3)<=off;  
 -- r e g i s t e r  
 process (clk, reset)  
 begin  
 if (reset='1') then  
 r_reg <= ( others => '0' ) ;  
 elsif (clk'event and clk='1') then  
 r_reg <= r_next;  
 end if ;  
 end process ;  
 --n e x t - s t a t e l o g i c  
 r_next <= ( others => '0' ) when r_reg=(M-1) else  
 r_reg + 1;  
 -- o u t p u t l o g i c  
 q <= std_logic_vector(r_reg);  
 output<=std_logic_vector(r_reg);  
 max_tick <= '1' when r_reg=(M-1) else '0' ;  
 display_unit:entity work.decRom16x7  
      Port map(address=>output,  
            d_out=>sseg);  
 end arch;  

DISPLAY MODULE

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 ----------------------------------------------------  
 -- Top level design  
 ----------------------------------------------------  
 entity decRom16x7 is  
      Port (address:      in STD_LOGIC_VECTOR(3 downto 0);  
            d_out: out STD_LOGIC_VECTOR(7 downto 0));  
 end decRom16x7;  
 ----------------------------------------------------  
 -- Internal Architecture  
 ----------------------------------------------------  
 architecture Behavioral of decRom16x7 is  
      signal delayVal: STD_LOGIC_VECTOR(6 downto 0);  
      begin  
      -- Use a with-select statement to light up relevant LEDs   
      -------------------------------------------------  
      -- Encoder   
      -------------------------------------------------  
      -- HEX-to-seven-segment decoder   
      -- segment encoding   
      --   0   
      --   ---   
      -- 5 |  | 1  
      --   --- <------6  
      -- 4 |  | 2  
      --   ---   
      --   3  
           with address select  
       delayVal <= --6542130  
                               "1000000" when "0000",--0  
                               "1110011" when "0001",--1  
                               "0101000" when "0010",--2  
                               "0110000" when "0011",--3  
                               "0010011" when "0100",--4  
                               "0010100" when "0101",--5  
                               "0000100" when "0110",--6  
                               "1110010" when "0111",--7  
                               "0000000" when "1000",--8  
                               "0010000" when "1001",--9  
                               "0000010" when "1010",--a  
                               "0000101" when "1011",--b  
                               "0101101" when "1100",--c  
                               "0100001" when "1101",--d  
                               "0001000" when "1110",--e  
                               "0001110" when others;--f  
                 --"1000000" when "0000",--0  
                               --"1111001" when "0001",--1  
                               --"0100100" when "0010",--2  
                               --"0110000" when "0011",--3  
                               --"0011001" when "0100",--4  
                               --"0010010" when "0101",--5  
                               --"0000010" when "0110",--6  
                               --"1111000" when "0111",--7  
                               --"0000000" when "1000",--8  
                               --"0010000" when "1001",--9  
                               --"0001000" when "1010",--a  
                               --"0000011" when "1011",--b  
                               --"1000110" when "1100",--c  
                               --"0100001" when "1101",--d  
                               --"0000110" when "1110",--e  
                               --"0001110" when "1111",--f  
                               --"XXXXXXX" when others;  
           d_out( 6 downto 0) <= delayVal after 14 ns;  
           d_out(7) <='1';  
 end Behavioral;  

UCF FILE

 NET "clk" LOC = "P54" ;  
 #8I/Os_2 (Input)  
 NET "reset" LOC = "p94" ;  
 #8I/Os_2 (Input)  
 NET "max_tick" LOC = "p52" ;  
 #16I/Os_1 (output)  
 NET "q[0]" LOC = "p126" ;  
 NET "q[1]" LOC = "p125" ;  
 NET "q[2]" LOC = "p124" ;  
 NET "q[3]" LOC = "p123" ;  
 #8I/Os_2 (cathods)  
 NET "an[0]" LOC = "p71" ;  
 NET "an[1]" LOC = "p75" ;  
 NET "an[2]" LOC = "p77" ;  
 NET "an[3]" LOC = "p82" ;  
 #16I/Os_2 seven segment display  
 NET "sseg[7]" LOC = "p60"  ;  
 NET "sseg[6]" LOC = "p63"  ;  
 NET "sseg[5]" LOC = "p67" ;  
 NET "sseg[4]" LOC ="p70"  ;  
 NET "sseg[3]" LOC ="p74" ;  
 NET "sseg[3]" LOC = "p76" ;  
 NET "sseg[2]" LOC = "p81"  ;  
 NET "sseg[0]" LOC = "p83" ;  

TUTORIAL ON HOW TO ADD CLOCK TIMING CONSTRAINTS IN A MODULE