VHDL Period counter of a square wave signal with oscilloscope test comparison Xilinx Spartan 3 development board

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PERIOD COUNTER VHDL CODE

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 use IEEE.numeric_std.ALL;  
 entity period_counter is  
 port (  
 clk , reset : in std_logic ;  
 start , si : in std_logic ;  
 ready , done_tick : out std_logic ;  
 prd : out std_logic_vector ( 9 downto 0)  
 );  
 end period_counter ;  
 architecture arch of period_counter is  
 constant CLK_MS_COUNT: integer := 3003; -- 1 ms t i c k  my clock speed 3Mhz period 3.33x10e-7 -------- so we want 3.33x10e-7 (x)= 1 ms  
 type state_type is ( idle , waite , count , done ) ;  
 signal state_reg , state_next : state_type ;  
 signal t_reg , t_next : unsigned (15 downto 0 ) ;  
 signal p_reg , p_next : unsigned ( 9 downto 0) ;  
 signal delay_reg : std_logic ;  
 signal edge : std_logic ;  
 begin  
 --s t a t e and d a t a r e g is t e r  
 process ( clk , reset )  
 begin  
 if reset = '1' then  
 state_reg <= idle ;  
 t_reg <= ( others => '0' ) ;  
 p_reg <= ( others => '0' ) ;  
 delay_reg <= '0' ;  
 elsif ( clk'event and clk = '1' ) then  
 state_reg <= state_next ;  
 t_reg <= t_next ;  
 p_reg <= p_next ;  
 delay_reg <= si ;  
 end if ;  
 end process ;  
 -- edge d e t e c t i o n c i r c u i t  
 edge <= ( not delay_reg ) and si ;  
 -- f s m d n e x t - s t a t e l o g i c / d a t a p a t h o p e r a t i o n s  
 process ( start , edge , state_reg , t_reg , t_next , p_reg )  
 begin  
 ready <= '0' ;  
 done_tick <= '0' ;  
 state_next <= state_reg ;  
 p_next <= p_reg ;  
 t_next <= t_reg ;  
 case state_reg is  
 when idle =>  
 ready <= '1' ;  
 if ( start = '1' ) then  
 state_next <= waite ;  
 end if ;  
 when waite => -- w a i t for t h e f i r s t edge  
 if ( edge = '1' ) then  
 state_next <= count ;  
 t_next <= ( others => '0' ) ;  
 p_next <= ( others => '0' ) ;  
 end if ;  
 when count =>  
 if ( edge = '1' ) then -- 2 n d edge a r r i v e d  
 state_next <= done ;  
 else -- o t h e r w i s e count  
 if (t_reg = CLK_MS_COUNT-1) then -- l m s t i c k  
 t_next <= ( others => '0' ) ;  
 p_next <= p_reg + 1;  
 else  
 t_next <= t_reg + 1;  
 end if ;  
 end if ;  
 when done =>  
 done_tick <= '1' ;  
 state_next <= idle ;  
 end case ;  
 end process ;  
 prd <= std_logic_vector(p_reg);  
 end arch ;  

CONSTRAINT FILE:

 NET "clk" LOC = "P54" ;  
 #8I/Os_2 (Input)  
 NET "reset" LOC = "p94" ;  
 NET "start" LOC = "p93" ;  
 NET "ready" LOC = "P52" ;  
 NET "done_tick" LOC = "P58";  
 NET "si" LOC = "p86" ;  
 #16I/Os_1 (output)  
 NET "prd[0]" LOC = "p126" ;  
 NET "prd[1]" LOC = "p125" ;  
 NET "prd[2]" LOC = "p124" ;  
 NET "prd[3]" LOC = "p123" ;  
 NET "prd[4]" LOC = "p122" ;  
 NET "prd[5]" LOC = "p117" ;  
 NET "prd[6]" LOC = "p116" ;  
 NET "prd[7]" LOC = "p113" ;  
 NET "prd[8]" LOC = "p112" ;  
 NET "prd[9]" LOC = "p106" ;