VHDL rising edge of a square wave signal detector Xilinx spartan 3 development board code and files

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 library ieee ;  
 use ieee.std_logic_1164.all;  
 entity edge_detect is  
 port (  
 clk,reset : in std_logic ;  
 level : in std_logic ;--555 timer  
 tick : out std_logic--yellow LED  
 ) ;  
 end edge_detect ;  
 architecture moore_arch of edge_detect is  
 type state_type is ( zero,edge,one ) ;--we have three states  
 signal state_reg,state_next :state_type ;  
 begin  
 -- s t a t e r e g i s t e r  
 process ( clk,reset)  
 begin  
 if(reset ='1' ) then -- if reset we stay in state 0  
 state_reg <= zero ;  
 elsif ( clk'event and clk = '1' ) then   
 state_reg <= state_next ;-- the next state becomes the current state until updated  
 end if ;  
 end process;  
 -- n e x t - s t a t e / o u t p u t logic  
 process ( state_reg , level ) --process depends of the current state and the input signal in this case coming from the 555 timer  
 begin  
 state_next <= state_reg ;-- we update the next state  
 tick <= '0' ; -- the tick output is initialized to 0-- yellow LED  
 case state_reg is -- depending of the current output  
 --rising edge  
 when zero =>   --input  state  
 if level = '1' then -- if input signal got to 1  
 state_next <= edge ; -- and edge has been detected  
 end if ;  
 when edge => -- if there is an edge   
 tick <= '1' ;-- we output a 1 in tick  
 if level = '1' then --if input signal is 1  
 state_next <= one; --next state is one  
 else        
 end if ;  
 --falling edge  
 if level = '0' then  -- if input signal becomes 0   
 state_next <= zero ; -- next state is 0  
 end if ;  
 when one =>  
 state_next <= zero ;  
 end case;  
 end process ;  
 end moore_arch;  

 NET "clk" LOC = "P54" ;  
 #8I/Os_2 (Input)  
 NET "reset" LOC = "p94" ;  
 NET "level" LOC = "p86" ;  
 #16I/Os_1 (output)  
 NET "tick" LOC = "p126" ;  

TUTORIAL ON HOW TO ADD CLOCK TIMING CONSTRAINTS IN A MODULE