library ieee ;
use ieee.std_logic_1164.all;
entity fifo_test is
port (
clk , reset : in std_logic;
btn: in std_logic_vector (1 downto 0 ) ;
sw: in std_logic_vector ( 2 downto 0 ) ;
led : out std_logic_vector ( 7 downto 0);
an : out std_logic_vector (3 downto 0);
sseg: out std_logic_vector ( 7 downto 0)
) ;
end fifo_test ;
architecture arch of fifo_test is
signal db_btn : std_logic_vector (1 downto 0) ;
signal empt : std_logic ;
signal fll ,cath,off: std_logic ;
signal sseg3,sseg2,sseg1,sseg0: std_logic_vector (3 downto 0) ;
signal rd_data: std_logic_vector (2 downto 0) ;
begin
--Enabling the first 7seg display
cath<='1';
off<='0';
an(0)<=cath;
an(1)<=off;
an(2)<=off;
an(3)<=off;
process(empt,fll)--if it is empty display e
begin
if (empt = '1' ) then
sseg0(3)<='0';
sseg0(2 downto 0 )<=rd_data after 5000 ms;
sseg0<="1110";
elsif (empt = '0' and fll = '0') then -- if it not empty display data
sseg0(3)<='0';
sseg0(2 downto 0 )<=rd_data;
else -- if it is full display F
sseg0(3)<='0';
sseg0(2 downto 0 )<=rd_data after 5000 ms;
sseg0<="1111";
---------------------------------------------
end if;
end process;
led(6)<=empt;
led(7)<=fll;
led ( 2 downto 0)<= rd_data;
-- deb(0)uncing c i r c u i t f (0) r b t n ( 0 )
btn_db_unit0 : entity work.debounce(exp_fsmd_arch)
port map ( clk => clk , reset => reset , sw=>btn(0),
db_level => open , db_tick=> db_btn(0));--rd debounce
-- deb(0)uncing c i r c u i t f (0) r b t n ( l )
btn_db_unit1: entity work.debounce(exp_fsmd_arch)
port map ( clk => clk , reset => reset , sw => btn(1) ,
db_level => open , db_tick => db_btn(1)) ;--wr debounce
--in s t a n t i a t e a 2 ^ 2 - b y - 3 f i f (0)
fifo_unit: entity work.fifo(arch)
generic map(B=>3, W=>2)
port map ( clk => clk , reset => reset ,
rd => db_btn(0) , wr=>db_btn(1) ,
w_data=>sw ,
empty=>empt,full =>fll,r_data => rd_data);
-- d is a b l e unused led s
led ( 5 downto 3 ) <= ( others =>'0' ) ;
--display module
display_unit:entity work.decRom16x7
Port map(address=>sseg0,
d_out=>sseg);
end arch;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity debounce is
port(
clk,reset : in std_logic;
sw:in std_logic;
db_level, db_tick: out std_logic
);
end debounce ;
architecture exp_fsmd_arch of debounce is--20ms is typically used to debounce --666.7hz -- 3Mhz
constant N : integer :=16; -- f i l t e r of (2 ^ N) * 1.49 ms = 40ms debounce interval -------1.49ms is the period of my clock with frequency 666.7 ----1/666.7=1.49ms (2^X) * 1.49ms =40ms ----2^X = 40ms/1.49ms--- 2^X= 27.97----- log2 (27.97)= X --- X= 4.80--- 2^5 * 1.49ms= 40ms
type state_type is ( zero , wait0 , one , wait1); --the signals below we create can have 4 states
signal state_reg , state_next : state_type; -- these signals
signal q_reg , q_next : unsigned ( N-1 downto 0 ) ;
signal q_load , q_dec , q_zero : std_logic ; --we use these signals as markers to go to the next stage in the design
begin
-- FSMD s t a t e C? d a t a r e g is t e r s
process (clk ,reset)
begin
if reset = '1' then -- if we reset we clear everything and wait for inputs
state_reg <= zero ; -- this is the state of the input
q_reg <= ( others => '0' ) ; --this is the state of the design which will progress depending of what happens with the input
elsif( clk'event and clk = '1' ) then --if rising edge of the clock
state_reg <= state_next ; -- state_next which is the signal that will be changing goes to the signal that wont change for the moment and that will be used for display until updated
q_reg <= q_next ; -- we update state of the design in q reg (nosrmally anything that is _next is the one that changes and stored in the one that doesnt change)
end if ;
end process ;
-- FSMD d a t a p a t h ( c o u n t e r ) n e x t - s t a t e
q_next<= (others => '1') when q_load = '1' else ---we decremetnt the states of the FSM if conditions met
q_reg - 1 when q_dec = '1' else
q_reg ;
q_zero<= '1' when q_next = 0 else '0' ;
--FSMD c o n t r o l p a t h n e x t - s t a t e
process ( state_reg ,sw,q_zero)
begin
q_load <= '0' ; --load the value of actual voltage state
q_dec <= '0' ; --decrement states
db_tick <= '0' ;-- if there has been a debounce 1
state_next <= state_reg ;
case state_reg is
--from 0 to 1
when zero => -- when is a 0
db_level <= '0' ; --voltage level is 0 transition to 1 below
if ( sw = '1') then -- if there is an input
state_next <= wait1; --wait some time until 1 hs been there for a while
q_load <= '1'; --load a 1
end if ;
when wait1=>
db_level <= '0' ; -- voltage level 0 as there has not been a real input
if ( sw = '1' ) then
q_dec <= '1'; -- decrement states
if ( q_zero = '1' ) then
state_next <= one ;
db_tick <= '1'; -- debounced
end if ;
else -- sw = '0'
state_next<= zero ; -- --REMAIN AS 0
end if ;
-- from 1 to 0
when one => --transition from 1 to 0
db_level <= '1'; -- if voltage level is 1 then wait until 0 is confirmed
if ( sw = '0' ) then
state_next <= wait0 ;
q_load <= '1';
end if ;
when wait0 =>
db_level <= '1'; -- voltage level set as 1 as input has been stable for a while
if ( sw = '0' ) then
q_dec <= '1';
if( q_zero = '1' ) then
state_next<= zero ;
end if ;
else
state_next<= one ;
end if ;
end case ;
end process ;
end exp_fsmd_arch ;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all ;
entity fifo is
generic (
B: natural:=8; -- number of b i t s
W: natural:=4 -- number o f a d d r e s s b i t s
);
port (
clk, reset: in std_logic;
rd, wr: in std_logic;
w_data: in std_logic_vector ( B - 1 downto 0) ;
empty, full : out std_logic;
r_data: out std_logic_vector ( B - 1 downto 0 )
);
end fifo;
architecture arch of fifo is
type reg_file_type is array (2**W-1 downto 0) of std_logic_vector ( B - 1 downto 0) ;
signal array_reg : reg_file_type ;
signal w_ptr_reg , w_ptr_next , w_ptr_succ : std_logic_vector (W-1 downto 0 ) ;
signal r_ptr_reg , r_ptr_next , r_ptr_succ:std_logic_vector ( W - 1 downto 0) ;
signal full_reg , empty_reg , full_next , empty_next :std_logic;
signal wr_op: std_logic_vector (1 downto 0 ) ;
signal wr_en : std_logic ;
begin
-- r e g is t e r f i l e
process (clk, reset)
begin
if (reset='1' ) then
array_reg <= ( others => ( others => '0' ) ) ;
elsif (clk'event and clk='1') then
if wr_en='1' then
array_reg(to_integer(unsigned(w_ptr_reg)))
<= w_data;
end if ;
end if ;
end process ;
-- r e a d p o r t
r_data <= array_reg(to_integer(unsigned(r_ptr_reg)));
--w r i t e e n a b l e d o n l y when FIFO is not f u l l
wr_en <= wr and ( not full_reg);
--
-- f if o c o n t r o l l o g i c
-- r e g is t e r f o r r e a d and w r i t e p o in t e r s
process (clk , reset)
begin
if (reset='1') then
w_ptr_reg <= ( others => '0' ) ;
r_ptr_reg <= ( others => '0' ) ;
full_reg <= '0' ;
empty_reg <= '1' ;
elsif(clk'event and clk='1') then
w_ptr_reg <= w_ptr_next ;
r_ptr_reg <= r_ptr_next ;
full_reg <= full_next;
empty_reg <= empty_next ;
end if ;
end process ;
-- s u c c e s s i v e p o in t e r v a l u e s
w_ptr_succ <= std_logic_vector (unsigned(w_ptr_reg)+1) ;
r_ptr_succ <= std_logic_vector(unsigned(r_ptr_reg)+1);
-- n e x t - s t a t e logic f o r r e a d and w r i t e p o in t e r s
wr_op <= wr & rd;
process (w_ptr_reg, w_ptr_succ ,r_ptr_reg ,r_ptr_succ ,wr_op,empty_reg , full_reg)
begin
w_ptr_next <= w_ptr_reg;
r_ptr_next <= r_ptr_reg;
full_next <= full_reg;
empty_next <= empty_reg ;
case wr_op is
when "00" => -- no op
when "01" => -- r e a d
if (empty_reg /= '1') then -- not e m p t y
r_ptr_next <= r_ptr_succ;
full_next <= '0' ;
if (r_ptr_succ=w_ptr_reg) then
empty_next <='1';
end if ;
end if ;
when "10" => -- w r i t e
if (full_reg /= '1' ) then -- if fifo not f u l l we write values
w_ptr_next <= w_ptr_succ;
empty_next <= '0' ;
if (w_ptr_succ=r_ptr_reg) then-- otherwise stop writing because is full, write pointer and read pointer point to the same place
full_next <='1';
end if ;
end if ;
when others => -- w r i t e / r e a d ;
w_ptr_next <= w_ptr_succ ;
r_ptr_next <= r_ptr_succ ;
end case ;
end process ;
-- out p u t
full <= full_reg;
empty <= empty_reg;
end arch;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
----------------------------------------------------
-- Top level design
----------------------------------------------------
entity decRom16x7 is
Port (address: in STD_LOGIC_VECTOR(3 downto 0);
d_out: out STD_LOGIC_VECTOR(7 downto 0));
end decRom16x7;
----------------------------------------------------
-- Internal Architecture
----------------------------------------------------
architecture Behavioral of decRom16x7 is
signal delayVal: STD_LOGIC_VECTOR(6 downto 0);
begin
-- Use a with-select statement to light up relevant LEDs
-------------------------------------------------
-- Encoder
-------------------------------------------------
-- HEX-to-seven-segment decoder
-- segment encoding
-- 0
-- ---
-- 5 | | 1
-- --- <------6
-- 4 | | 2
-- ---
-- 3
with address select
delayVal <=
"1111001" when "0000",--0 "0100100" when "0001",--1
"0101000" when "0010",--2
"0100100" when "0011",--3
"0011001" when "0100",--4
"0010010" when "0101",--5
"0000010" when "0110",--6
"1111000" when "0111",--7
"0000000" when "1000",--8
"0010000" when "1001",--9
"0001000" when "1010",--a
"0000011" when "1011",--b
"1000110" when "1100",--c
"0100001" when "1101",--d
"0000110" when "1110",--e
"0001110" when others;--f
d_out( 6 downto 0) <= delayVal after 14 ns;
d_out(7) <='1';
end Behavioral;
NET "reset" LOC = "P87" ;
#8I/Os_2 (rd/wr)
NET "btn[0]" LOC = "p94" ;#rd
NET "btn[1]" LOC = "p93" ;#wr
#8I/Os_2 (Input) binary format
NET "sw[0]" LOC = "p92" ;
NET "sw[1]" LOC = "p91" ;
NET "sw[2]" LOC = "p88" ;
#16I/Os_2 to represnet the binary numbers, full and empty
NET "led[0]" LOC = "p126" ;
NET "led[1]" LOC = "p125" ;
NET "led[2]" LOC = "p124" ;
NET "led[3]" LOC = "p123" ;
NET "led[4]" LOC = "p122" ;
NET "led[5]" LOC = "p117" ;
NET "led[6]" LOC = "p116" ;
NET "led[7]" LOC = "p113" ;
#Created by Constraints Editor (xc3s250e-tq144-4) - 2017/06/20
NET "clk" LOC = "p54"; # coming from a signal generator
#TIMESPEC TS_clk = PERIOD "clk" 50 MHz HIGH 50%;
#Created by Constraints Editor (xc3s250e-tq144-4) - 2017/06/20
#NET "clk" LOC = "p54";
#TIMESPEC TS_clk = PERIOD "clk" 50 MHz HIGH 50%;
#8I/Os_2 (cathods)
NET "an[0]" LOC = "p71" ;
NET "an[1]" LOC = "p75" ;
NET "an[2]" LOC = "p77" ;
NET "an[3]" LOC = "p82" ;
#16I/Os_2 seven segment display
NET "sseg[7]" LOC = "p60" ;
NET "sseg[6]" LOC = "p63" ;
NET "sseg[5]" LOC = "p67" ;
NET "sseg[4]" LOC ="p70" ;
NET "sseg[3]" LOC ="p74" ;
NET "sseg[2]" LOC = "p76" ;
NET "sseg[1]" LOC = "p81" ;
NET "sseg[0]" LOC = "p83" ;
TUTORIAL ON HOW TO ADD CLOCK TIMING CONSTRAINTS IN A MODULE
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