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library ieee;
use ieee . std_logic_1164.all;
entity stop_watch_test is
port (
clk: in std_logic;
btn: in std_logic_vector (3 downto 0) ;-- btn 1 to go and 0 to clear the count
an: out std_logic_vector (3 downto 0) ;-- to enable cathode
sseg : out std_logic_vector ( 7 downto 0)-- display
) ;
end stop_watch_test;
architecture arch of stop_watch_test is
signal d2, d1 , d0 : std_logic_vector (3 downto 0) ; --address where to get the hexadecimal display code
begin
disp_unit : entity work.disp_hex_mux -- display module with hexadecimal values port map
port map(
clk=>clk, reset=>'0', -- clear and reset
hex3=>"0000" , hex2=>d2, --last display disabled set to 0000
hex1=>d1 , hex0=>d0,
dp_in=>"1011" , an=>an, sseg=>sseg) ; --place to put the decimal point
watch_unit : entity work.stop_watch(cascade_arch)-- stop watch module port map
port map(
clk=>clk, go=>btn(1) , clr=>btn(0), --go to start the count and clear
d2 =>d2, d1=>d1, d0=>d0 ) ; --hexadecimal values sent to display
end arch;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all ;
entity disp_hex_mux is
port(
clk, reset: in std_logic;
hex3, hex2, hex1 ,hex0 : in std_logic_vector (3 downto 0 ) ;
dp_in : in std_logic_vector (3 downto 0) ;
an: out std_logic_vector (3 downto 0) ;
sseg : out std_logic_vector ( 7 downto 0)
);
end disp_hex_mux ;
architecture arch of disp_hex_mux is
-- each 7 - s e g l e d enabled ( 2 ^ 3 / 4 ) * 2 . 5 n s
constant N: integer :=3;-- time we want the display to hold on visible
signal q_reg , q_next : unsigned (N-1 downto 0) ;
signal sel : std_logic_vector (1 downto 0) ;
signal hex: std_logic_vector (3 downto 0) ;
signal dp: std_logic;
begin
-- register to switch between cathodes
process (clk , reset)
begin
if reset='1' then
q_reg <= ( others => '0' ) ;
elsif (clk'event and clk='1') then
q_reg <= q_next;
end if ;
end process;
-- n e x t - s t a t e l o g i c for t h e c o u n t e r
q_next <= q_reg + 1 ;
-- 2 MSBs o f c o u n t e r t o c o n t r o l 4 - t o - l m u l t i p l e x in g
sel <= std_logic_vector (q_reg(N-1 downto N-2)) ;
process (sel , hex0 , hex1 , hex2, hex3, dp_in)
begin --seven segment display multiplexed
case sel is
when "00" =>
an <= "0001" ;
hex <= hex0;
dp <= dp_in(0);
when "01" =>
an <= "0010" ;
hex <= hex1;
dp <= dp_in(1);
when "10" =>
an <= "0100" ;
hex <= hex2;
dp <= dp_in(2);
when others =>
an <= "1000" ;
hex <= hex3;
dp <= dp_in(3);
end case ;
end process;
--hex - t o - 7- s e g in e IZ t I e d decoding
-- Use a with-select statement to light up relevant LEDs
-------------------------------------------------
-- Encoder
-------------------------------------------------
-- HEX-to-seven-segment decoder
-- segment encoding
-- 0
-- ---
-- 5 | | 1
-- --- <------6
-- 4 | | 2
-- ---
-- 3
with hex select --6542130
sseg(6 downto 0)<= "1111001" when "0000",--0
"0100100" when "0001",--1
"0101000" when "0010",--2
"0100100" when "0011",--3
"0011001" when "0100",--4
"0010010" when "0101",--5
"0000010" when "0110",--6
"1111000" when "0111",--7
"0000000" when "1000",--8
"0010000" when "1001",--9
"0001000" when "1010",--a
"0000011" when "1011",--b
"1000110" when "1100",--c
"0100001" when "1101",--d
"0000110" when "1110",--e
"0001110" when others;--f
--d e c i m a l p o in t
sseg(7) <= dp;
end arch;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity stop_watch is
port (
clk : in std_logic;
go , clr: in std_logic;
d2, d1 , d0: out std_logic_vector (3 downto 0)--three seven segment displays to be used
) ;
end stop_watch;
architecture cascade_arch of stop_watch is
constant DVSR: integer :=10; --controls how fast the count is
signal ms_reg , ms_next : unsigned (22 downto 0 ) ;
signal d2_reg, d1_reg , d0_reg : unsigned (3 downto 0) ;
signal d2_next , d1_next , d0_next : unsigned (3 downto 0) ;
signal d1_en , d2_en, d0_en: std_logic;
signal ms_tick , d0_tick, d1_tick: std_logic ;
begin
--re g is t e r
process (clk)
begin
if (clk'event and clk= '1' ) then
ms_reg <= ms_next;--ms reg actual state of the signal ---------ms_next signal being changed depending of the conditions
d2_reg <= d2_next;
d1_reg <= d1_next;
d0_reg <= d0_next;
end if ;
end process ;
--n e x t - s t a t e l o g i c
--0 . 1 s e e t i c k g e n e r a t or : mod-10
ms_next <=-- counter becomes 0 when clear is 1 or when msreg=10 otherwise keep counting
(others =>'0') when clr='1' or
(ms_reg=DVSR and go='1') else
ms_reg + 1 when go='1' else
ms_reg ;
ms_tick <= '1' when ms_reg=DVSR else '0' ; -- the counter reached 10 so we mark it with a 1
--0 . 1 s e e c o u n t e r
d0_en <= '1' when ms_tick='1' else '0' ; -- when tick has been checked we enable the first display
d0_next <= -- sned values to fist display
"0000" when (clr='1' ) or (d0_en='1' and d0_reg=9) else -- display 0 if clear or if cout reached 9
d0_reg + 1 when d0_en='1' else -- otherwise increase the counte and display
d0_reg ; -- otherwise keep the value unchanged
d0_tick <= '1' when d0_reg=9 else '0' ; -- when count reaches 9 mark the display with a tick
--is e e c o u n t e r
d1_en <= '1' when ms_tick='1' and d0_tick='1' else '0'; -- when fist display has been marked with a tick then enable display 2
d1_next <= --send values to second display
"0000" when (clr='1') or (d1_en='1' and d1_reg=9) else
d1_reg + 1 when d1_en='1' else
d1_reg ;
d1_tick <= '1' when d1_reg=9 else '0' ;
--I 0 s e e c o u n t e r
d2_en <=
'1' when ms_tick='1' and d0_tick='1' and d1_tick='1' else
'0';
d2_next <=
"0000" when (clr='1') or (d2_en='1' and d2_reg=9) else
d2_reg + 1 when d2_en='1' else
d2_reg ;
--o u t p u t l o g i c
d0 <= std_logic_vector (d0_reg) ;
d1 <= std_logic_vector(d1_reg);
d2 <= std_logic_vector(d2_reg);
end cascade_arch;
NET "clk" LOC = "P54" ;
#8I/Os_2 (Input)
NET "btn[0]" LOC = "p94" ;
NET "btn[1]" LOC = "p93" ;
NET "btn[2]" LOC = "p92" ;
NET "btn[3]" LOC = "p91" ;
#8I/Os_2 (Input)
NET "an[0]" LOC = "p71" ;
NET "an[1]" LOC = "p75" ;
NET "an[2]" LOC = "p77" ;
NET "an[3]" LOC = "p82" ;
#16I/Os_2
NET "sseg[7]" LOC = "p60" ;
NET "sseg[6]" LOC = "p63" ;
NET "sseg[5]" LOC = "p67" ;
NET "sseg[4]" LOC ="p70" ;
NET "sseg[3]" LOC ="p74" ;
NET "sseg[2]" LOC = "p76" ;
NET "sseg[1]" LOC = "p81" ;
NET "sseg[0]" LOC = "p83" ;
TUTORIAL ON HOW TO ADD CLOCK TIMING CONSTRAINTS IN A MODULE
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