8 bits Free run binary counter VHDL XIlinx spartan 3 board implementation and code

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 library ieee;  
 use ieee.std_logic_1164.all ;  
 use ieee. numeric_std.all;  
 entity free_run_bin_counter is  
 generic (N:integer:=8);  
 port(  
 clk, reset: in std_logic;  
 max_tick: out std_logic;  
 q: out std_logic_vector (N-1 downto 0)  
 ) ;  
 end free_run_bin_counter ;  
 architecture arch of free_run_bin_counter is  
 signal r_reg: unsigned(N-1 downto 0 ) ;  
 signal r_next : unsigned (N-1 downto 0) ;  
 begin  
 -- r e g i s t e r  
 process (clk, reset)  
 begin  
 if (reset='1') then  
 r_reg <= ( others => '0' ) ;  
 elsif(clk'event and clk='1') then  
 r_reg <= r_next;  
 end if ;  
 end process;  
 --n e x t - s t a t e l o g i c  
 r_next <= r_reg + 1;  
 --o u t p u t l o g i c  
 q<= std_logic_vector(r_reg);  
 max_tick <= '1' when r_reg=(2**N-1) else '0' ;--r_reg=(2**N-1) means 2 to the power of N then minus 1 = 255 11111111  
 end arch;  

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