VHDL Sign Magnitud adder circuit test and code Xilinx spartan 3 board

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 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 use IEEE.NUMERIC_STD.ALL;  
 -- Uncomment the following library declaration if instantiating  
 -- any Xilinx primitives in this code.  
 --library UNISIM;  
 --use UNISIM.VComponents.all;  
 entity sign_mag_add is  
 generic(N: integer:=4);  
   Port ( a : in STD_LOGIC_vector(n-1 downto 0);  
       b : in STD_LOGIC_vector(n-1 downto 0);  
       sum : out STD_LOGIC_vector(n-1 downto 0));  
 end sign_mag_add;  
 architecture Behavioral of sign_mag_add is  
 signal mag_a , mag_b : unsigned(N-2 downto 0 ) ;  
 signal mag_sum , max , min: unsigned(N-2 downto 0) ;  
 signal sign_a , sign_b , sign_sum: std_logic;  
 begin  
 mag_a <= unsigned (a(N-2 downto 0 )) ;  
 mag_b <= unsigned(b(N-2 downto 0 ) ) ;  
 sign_a <= a(N-1);  
 sign_b <= b(N-1);  
 --s o r t a c c o r d i n g t o m a g n i t u d e  
 process (mag_a ,mag_b , sign_a, sign_b)  
 begin  
 if mag_a > mag_b then  
 max <= mag_a;  
 min <= mag_b;  
 sign_sum <= sign_a;  
 else  
 max <= mag_b;  
 min <= mag_a;  
 sign_sum <= sign_b;  
 end if;  
 end process;  
 -- a d d / s u b m a g n i t u d e  
 mag_sum <= max + min when sign_a=sign_b   
 else  
 max - min;  
 --form o u t p u t  
 sum <= std_logic_vector(sign_sum & mag_sum);  
 end Behavioral;