Structural Microprocessor design VHDL Controlled Datapath Ones counter and Ones shifter microprogram ciruit test Xilinx

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

Lab Sheets:

http://viahold.com/y37

Lab guide, Data path and control words, Controller and next state logic to manipulate the datapath:
https://yadi.sk/d/Xe62M3Ds3MoVMD

Final design files download:

VHDL Xilinx ISE files

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

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CONTROL WORDS USED IN THE DATAPATH (ONES COUNTER) refer to the learning material

Lab guide, Data path and control words, Controller and next state logic to manipulate the datapath:

https://yadi.sk/d/Xe62M3Ds3MoVMD

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 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 use IEEE.STD_LOGIC_ARITH.ALL;  
 use IEEE.STD_LOGIC_UNSIGNED.ALL;  
 entity ONESHIFTER_CONTROLLED_DATA_PATH is  
 generic(n:positive:=4);  
   Port ( start :        in STD_LOGIC;  
       alt : in STD_LOGIC;  
                 clk : in STD_LOGIC;  
                 asynchronousreset : in STD_LOGIC;  
       datain : in STD_LOGIC_VECTOR (3 downto 0);  
       done : out STD_LOGIC;  
       dataout : inout STD_LOGIC_VECTOR (3 downto 0));  
 end ONESHIFTER_CONTROLLED_DATA_PATH;  
 architecture Behavioral of ONESHIFTER_CONTROLLED_DATA_PATH is  
 component CONTROLLER   
 generic(n:positive:=4);  
   Port ( start : in STD_LOGIC;  
       datanotzero : in STD_LOGIC;  
                 alt :in std_logic;  
       clk : in STD_LOGIC;  
       asynchronousreset : in STD_LOGIC;  
       datapathcontrol : out STD_LOGIC_VECTOR (19 downto 0);  
       done : out STD_LOGIC);  
 end component;  
 component DATA_PATH   
 generic(n:positive:=4);  
   Port ( Input : in STD_LOGIC_VECTOR (3 downto 0);  
       S : in STD_LOGIC;  
       Write_address : in STD_LOGIC_VECTOR (2 downto 0);  
       Write_enable : in STD_LOGIC;  
       Read_address_A : in STD_LOGIC_VECTOR (2 downto 0);  
       Read_Enable_A : in STD_LOGIC;  
       Read_address_B : in STD_LOGIC_VECTOR (2 downto 0);  
       Read_Enable_B : in STD_LOGIC;  
       Function_arith_or_logic : in STD_LOGIC_VECTOR (2 downto 0);  
       G : in STD_LOGIC_VECTOR (2 downto 0);  
       Status : out STD_LOGIC;  
       en : in STD_LOGIC;  
       clk : in STD_LOGIC;  
       Output : out STD_LOGIC_VECTOR (3 downto 0));  
 end component;  
 SIGNAL controlwords : std_logic_vector(19 downto 0);  
 SIGNAL datanotzero : std_logic;  
 begin  
                --datanotzero comes from data path 0 (output register part)  
 firstpart: CONTROLLER port map(start,datanotzero,alt,clk,asynchronousreset,controlwords,done);  
 secondpart: DATA_PATH port map(datain,controlwords(19),controlwords(18 downto 16),controlwords(15),controlwords(14 downto 12),controlwords(11),controlwords(10 downto 8),controlwords(7),controlwords(6 downto 4),controlwords(3 downto 1),datanotzero,controlwords(0),clk,dataout);  
 end Behavioral;