library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decRom2 is
Port ( address: in STD_LOGIC_VECTOR(3 downto 0);
condition_select: out STD_LOGIC_VECTOR(1 downto 0);
Functions: out STD_LOGIC_VECTOR(1 downto 0);
d_out: out STD_LOGIC_VECTOR(19 downto 0);
done : out STD_LOGIC;
Branch_ADDRESS_M : out STD_LOGIC_VECTOR(3 downto 0));
end decRom2;
-- Internal Architecture
architecture Behavioral of decRom2 is
signal delayVal: STD_LOGIC_VECTOR(19 downto 0);
--------ALU operation------------------------------
-- 000 Complement A
-- 001 And
-- 010 XOR
-- 011 or
-- 100 Increment A
-- 101 Add A+B
-- 110 Decrement A
-- 111 Subtract A-B
--------Shifter operation------------------------------
-- 000 pass
-- 001 rotate left
-- 010 shift left input 0
-- 011 shift left input 1
-- 100 pass
-- 101 rotate right
-- 110 shift right input 0
-- 111 shift right input 1
begin
with address select --Input enable 1bit,address where to write 3bits,write address enable 1bit, read address A 3bits,enableaddress A 1bit,read address B 3bits,enable address B 1bit, ALU operation 3bits, shift rotate 3 bits,output enable 1 bit
delayVal <= "0---0---0---0------0" when "0000",
"10001---0---0------0" when "0001",
"00101000100010100000" when "0010",
"00011010100001000000" when "0011",--0001
"00111000100110010000" when "0100",--0010
"00101010101111010000" when "0101",--0100
"00001000100010011100" when "0110",--0100
"00000010101010010001" when "0111",--1000
"00000000000000000000" when others;
d_out <= delayVal after 14 ns;
--FUNCTION---VALUE-----COUNTER------------------------------------------
--------------------
----CA---- ---00---- LC=> 0 EN=>1 Count alwas go to next state n+1
----CC---- ---01---- LC=> 0 EN=>condition Next state if condition is true
----BC---- ---10---- LC=> 1 EN=>contition jump to random condition m if condition is true otherwise remain there in n
----CBC--- ---11---- LC=> condition EN=>1 Jum to another state if true otherwise continue n+1 state
-- DECIDE WHICH BRANCH FUNCTION TO USE
with address select
Functions <= "01" when "0000",
"00" when "0001",
"00" when "0010",
"00" when "0011",
"00" when "0100",
"00" when "0101",
"11" when "0110",
"10" when "0111",
"00" when others;
--CONDITION---VALUE--
--------------------
----'1'---- ---00---- Condition alwas true continue
----Start---- ---01---- Start
----Datanot zero ---10---- If calculation are not finish loop to other states
----not used--- ---11----
--DECIDE WHICH STATE TO GO IN WITH
with address select
condition_select <= "01" when "0000",
"--" when "0001",
"--" when "0010",
"--" when "0011",
"--" when "0100",
"--" when "0101",
"10" when "0110",
"00" when "0111",
"00" when others;
-- IS PROGRAM DONE?
with address select
done <= '0' when "0000",
'0' when "0001",
'0' when "0010",
'0' when "0011",
'0' when "0100",
'0' when "0101",
'0' when "0110",
'1' when "0111",
'0' when others;
-- SELECT NEXT ADDRESS IF BRANCHING
with address select
Branch_ADDRESS_M <= "----" when "0000",
"----" when "0001",
"----" when "0010",
"----" when "0011",
"----" when "0100",
"----" when "0101",
"0100" when "0110",
"0000" when "0111",
"0000" when others;
end Behavioral;
Friday, 19 May 2017
Decoder ROM instructions for the ones counter VHDL microcontroller structural design Xilinx
Subscribe to:
Post Comments (Atom)
No comments:
Post a Comment