VHDL Static RAM cell Structural design code plus test in circuit ISE Xilinx

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

Parts working on now:

This is another components which will be used to construct the datapath. Refer to the lab sheets:

VHDL code:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 use IEEE.STD_LOGIC_ARITH.ALL;  
 use IEEE.STD_LOGIC_UNSIGNED.ALL;  
 entity static_RAM_cell is  
   Port ( Data_in : in STD_LOGIC;  
       Cell_select : in STD_LOGIC;  
       Write_enable : in STD_LOGIC;  
       Data_out : out STD_LOGIC);  
 end static_RAM_cell;  
 architecture Behavioral of static_RAM_cell is  
 component D_flipflop is  
 port (d, clk, reset, preset : in std_logic;  
           q,qnot: out std_logic);  
 end component;  
 component tri_buff is  
 Port ( Input : in std_logic;  
       enable : in std_logic;  
       Output : out std_logic);  
                 end component;  
 component andgate is  
 Port ( a : in std_logic;  
       b : in std_logic;  
       f : out std_logic);  
                 end component;  
 signal clk_sig, dummy, Q_sig: STD_LOGIC;  
 begin  
 ANDIT: andgate port map (Write_enable, Cell_select,     clk_sig ) ; -- decides if the output is read or write   
 DIT: D_flipflop port map (Data_in,clk_sig,'0' , '0', Q_sig, dummy ) ;      -- this will hold the value at Q  
 TRI_IT: tri_buff port map (Q_sig, Cell_select , Data_out );      -- if cell select is 0 then Qcant be read and high impedance is shown  
 end Behavioral;  

Component ( D flip flop ) code in the video description

Component ( Tri state buffer ) code in the video description

Component ( and gate ) code in the video description

TUTORIAL ON HOW TO ADD CLOCK TIMING CONSTRAINTS IN A MODULE