electronics blog: VHDL 8 x 4 Static RAM Structural design code plus test in circuit ISE Xilinx

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

Parts working on now:

This is another components which will be used to construct the controlled datapath. Refer to the lab sheets:

VHDL 8 x 4 Static RAM:

VHDL code:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 use IEEE.STD_LOGIC_ARITH.ALL;  
 use IEEE.STD_LOGIC_UNSIGNED.ALL;  
 --ENTITY  
 entity eight_by_four_sram is  
  Port ( address : in std_logic_vector(2 downto 0);  
       read_notwrite : in std_logic;  
       chip_select : in std_logic;  
       data_inout : inout std_logic_vector(3 downto 0));  
 end eight_by_four_sram;  
 -- ARCHITECTURE  
 architecture Behavioral of eight_by_four_sram is  
 -- COMPONENTS  
 component three_to_eight_decoder  
   Port (      OE : in std_logic;  
                      address : in std_logic_vector(2 downto 0);  
                     O_outputs : out std_logic_vector(7 downto 0));  
 end component;  
 component mxn_bit_Static_RAM_cell is  
  generic( n : positive := 4 ; m : positive := 8) ;  
           Port ( Data_in : in STD_LOGIC_VECTOR (n-1 downto 0);  
       Select_lines : in STD_LOGIC_VECTOR (m-1 downto 0);  
       Write_enable : in STD_LOGIC;  
       Data_out : out STD_LOGIC_VECTOR (n-1 downto 0));  
 end component;  
 component nbittristatebuffer is       
       generic ( n : positive := 4);  
   Port ( datain : in STD_LOGIC_VECTOR (n-1 downto 0);  
       enable : in STD_LOGIC;  
       output : out STD_LOGIC_VECTOR (n-1 downto 0));  
 end component;  
 -- SIGNALS  
 signal select_lines : std_logic_vector (7 downto 0);  
 signal array_to_tribuff : std_logic_vector (3 downto 0);  
 signal array_enable, buff_enable : std_logic;  
 begin  
 -- LOGIC ASSIGNMENTS:  
 array_enable <= (not read_notwrite) and chip_select ;  
 buff_enable <= read_notwrite and chip_select ;  
 -- DEVICE INSTANCES  
 decode : three_to_eight_decoder port map ('1', address, select_lines);  
 ramarray : mxn_bit_Static_RAM_cell port map (data_inout, select_lines, array_enable, array_to_tribuff);  
 tribuff : nbittristatebuffer generic map (4) port map (array_to_tribuff, buff_enable, data_inout);  
 end Behavioral;

Component ( 3 to 8 decoder ) code in the video description