VHDL m x n Static RAM cell array Structural design code plus test in circuit ISE Xilinx

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

Parts working on now:

This is another components which will be used to construct the datapath. Refer to the lab sheets:

VHDL code:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 use IEEE.STD_LOGIC_ARITH.ALL;  
 use IEEE.STD_LOGIC_UNSIGNED.ALL;  
 entity mxn_bit_Static_RAM_cell is  
  generic( n : positive := 4 ; m : positive := 4) ;  
           Port ( Data_in : in STD_LOGIC_VECTOR (n-1 downto 0);  
       Select_lines : in STD_LOGIC_VECTOR (m-1 downto 0);  
       Write_enable : in STD_LOGIC;  
       Data_out : out STD_LOGIC_VECTOR (n-1 downto 0));  
 end mxn_bit_Static_RAM_cell;  
 architecture Behavioral of mxn_bit_Static_RAM_cell is  
 component static_RAM_cell is  
   Port ( Data_in : in STD_LOGIC;  
       Cell_select : in STD_LOGIC;  
       Write_enable : in STD_LOGIC;  
       Data_out : out STD_LOGIC );  
 end component;  
 begin  
           inst : for i in m-1 downto 0 generate           -- this loop conveys the rows  
                inst2 : for j in n-1 downto 0 generate      -- this loop shows number of elements in the row  
                     SRAMIT: static_RAM_cell port map (Data_in(j), Select_lines(i), Write_enable, Data_out(j));           -- completes each ram in each row  
           end generate;               --time to change row  
                end generate;                -- mxn array is complete  
 end Behavioral;  

Component ( Static RAM cell ) code in the video description

TUTORIAL ON HOW TO ADD CLOCK TIMING CONSTRAINTS IN A MODULE