FPGA Verilog Police siren sound in speaker and PWM LEDs Xilinx Spartan 3 development board

module siren(clk,speaker,clk_measure,LED_RED,LED_BLUE);
input clk;

output clk_measure;
output speaker;
output LED_RED;
output LED_BLUE;

reg [23:0]count;
wire clock_div;
reg [23:0] cnt;

//Clock division 50Mhz input => output 25Mhz
always @(posedge clk) begin
count <= count+1;
end
assign clock_div = count[0];

assign clk_measure = clock_div; //probe to measure the clock speed in oscilloscope


//Siren
parameter clkdivider = 25000000/440/2;

reg [23:0] tone;
always @(posedge clock_div) tone <= tone+1;

reg [14:0] counter;
always @(posedge clock_div) if(counter==0) counter <= (tone[23] ? clkdivider-1 : clkdivider/2-1); else counter <= counter-1;

reg speaker;
always @(posedge clock_div) if(counter==0) speaker <= ~speaker;


//PWM LEDs
always @(posedge clock_div) begin
cnt<=cnt+1;
end
wire [3:0] PWM_input = cnt[22] ? cnt[21:18] : ~cnt[21:18];
reg [4:0] PWM;
always @(posedge clock_div) PWM <= PWM[3:0]+PWM_input;

assign LED_RED = PWM[4];
assign LED_BLUE = ~PWM[4];

endmodule

#Created by Constraints Editor (xc3s250e-tq144-4) - 2018/01/15
NET "clk" LOC = "P129" ;  #TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 50 MHz HIGH 50%;

NET "clk_measure" LOC = "p54" ;
NET "speaker" LOC = "p94" ;
NET "LED_RED" LOC = "p93" ;
NET "LED_BLUE" LOC = "p92" ;